近年來，低功耗的元件開始逐漸被重視，穿隧式電晶體為其中一個候選元件之一，其具有極陡峭的次臨界擺幅與較低的漏電流，但因傳導機制的因素，使其導通電流比傳統薄膜式電晶體來的低，為其重大缺點之一。
在本實驗中，先探討主動層厚度對傳統薄膜電晶體之影響，再討論對於多晶矽穿隧式電晶體，主動層厚度分別為1000Å與500Å。在傳統薄膜電晶體中會發現1000Å的Ion與S.S.較500Å佳，原因為通道結晶性較佳及串聯電阻效應，但1000Å的Ioff也較高，是因為接面體積較500Å大；而對於多晶矽穿隧式電晶體而言，500Å的元件不管是Ion、Ioff還是S.S.都比1000Å佳，歸因為因主動層厚度較薄，垂直電場變大，使閘極控制能力變好，Ion及S.S.因此獲得改善，且由於500Å之接面體積較小，使其漏電流亦較低。
除此之外，也比較了不同主動層厚度對於通道微縮與變溫時之多晶矽穿隧式電晶體之電性，發現不管在通道微縮或是變溫時，500Å之多晶矽穿隧式電晶體其電性皆比1000Å佳，也就是說，在通道厚度變薄後，雖然缺陷亦會變多，但此時垂直電場會開始成為主導方，並改善多晶矽穿隧式電晶體之電性。

In recent years, low power devices such as tunneling field-effect transistor (TFET) have attracted much attention, which have steep subthreshold swing and low leakage current, but because of the current mechanism, the on-state current for TFET is general much lower than that of inversion mode devices.
In this thesis, we will discuss traditional thin-film transistor (TFT) with different active layer thickness, and then turn to the effect of TFETs. The various thicknesses we discuss for active layer are 1000Å and 500Å. In traditional TFT, we found that the thicker active layer devices have better on-state current and S.S., these characteristics are attributed to channel crystallinity and series resistance effect, but the thicker active layer TFTs also have higher off-state current owing to larger junction volume ; For TFETs, we found that the thinner active layer devices have batter on-state current, S.S., and lower off-state current, it is due to the thinner active layer devices have much larger vertical electric field so that the bending of band gap between channel and source could be more obvious, and the junction volume of thinner active layer devices are also smaller, therefore, the TFETs with thinner active layer devices have lower off-state current.
In addition, we also compared the influence of various channel length and temperature for the different active layer thickness TFETs, and we found that whatever the channel length or temperature is, the thinner active layer devices shows the better performance, that is, although the thinner active layer will have more defects after channel crystallization. However, the vertical electric field will begin to become the dominant mechanism, so that the performance of the thinner one is better than the thicker one.

目錄

論文議定書 i
致謝 ii
摘要 iii
Abstract iv
目錄 v
第一章 緒論與介紹 1
1-1 前言 1
1-2 實驗動機 2
1-3 矽之晶向排列 2
1-4 固相結晶法(Solid Phase Crystallization, SPC) 3
1-5 多晶矽薄膜電晶體(Poly-Si Thin-Film Transistor, TFT) 3
1-6 短通道效應(Short Channel Effect, SCE) 4
1-6-1 汲極導致能障降低(Drain-Induced Barrier Lowering, DIBL) 4
1-6-2 擊穿崩潰(Punch Through) 4
1-7 穿隧式場效電晶體(Tunneling Field-Effect Transistor, TFET) 4
1-8 穿隧式場效電晶體電流機制 5
1-8-1 產生與複合電流(Generation and Recombination Current) 5
1-8-2 陷阱輔助穿隧(Trap-Assisted Tunneling, TAT) 6
1-8-3 能帶間穿隧(Band-to-Band Tunneling, BTBT) 6
第二章 實驗步驟與流程 14
2-1 元件製作 14
2-2 元件電性參數萃取 15
2-2-1 臨界電壓(Threshold Voltage, Vth) 15
2-2-2 平帶電壓(Flat-Band Voltage, VFB) 16
2-2-3 次臨界擺幅(Subthreshold Swing, S.S.) 16
2-2-4 開啟電流(On-State Current, Ion) 16
2-2-5 關閉電流(Off-state Current, Ioff) 16
2-2-6 晶粒邊界陷阱能態(Grain Boundary Trap State, NGB) 17
2-2-7 界面陷阱能態(Interface Trap State, Nit) 17
第三章 結果與討論 23
3-1 傳統薄膜電晶體與穿隧式電晶體 23
3-2 傳統薄膜電晶體之主動層厚度效應 23
3-3 不同主動層厚度之多晶矽薄膜電晶體變溫影響 25
3-4 多晶矽穿隧式電晶體之主動層厚度效應 25
3-5 不同主動層厚度之多晶矽穿隧式電晶體通道調變 26
3-6 不同主動層厚度之多晶矽穿隧式電晶體變溫影響 27
第四章 結論 39
參考文獻 41
 
圖目錄

圖1- 1晶向排列[3]。 8
圖1- 2 傳統薄膜電晶體構造圖。 8
圖1- 3 MOSFET操作原理[3] (a)MOSFET構造圖(b)關閉狀態(c)弱反轉時(d)開啟狀態。 9
圖1- 4汲極導致能障降低[4] 9
圖1- 5 穿隧式電晶體構造圖 10
圖1- 6 穿隧式電晶體能帶圖-開啟狀態[5] 10
圖1- 7 穿隧式電晶體能帶圖-關閉狀態[5] 11
圖1- 8 穿隧式電晶體能帶圖-反向導通[5] 11
圖1- 9 穿隧式電晶體電流機制[7] 12
圖1- 10 SRH機制種類[3] 12
圖1- 11 陷阱輔助穿隧能帶圖[8] 13
圖1- 12 能帶間穿隧能帶圖 [9] 13

圖2- 1 矽基板 18
圖2- 2 矽基板上長一層濕式氧化層 18
圖2- 3 沉積非晶矽並定義出主動區 18
圖2- 4 固相結晶後非晶矽轉變晶向成多晶矽 19
圖2- 5 離子佈植後形成N+ 19
圖2- 6離子佈植後形成P+ 19
圖2- 7 使用電子槍蒸鍍系統沉積二氧化矽 20
圖2- 8 沉積鈦後並蝕刻出金屬閘極 20
圖2- 9 蝕刻出接觸窗 21
圖2- 10 沉積鋁矽銅並蝕刻出襯墊 21
圖2- 11 薄膜電晶體之製程圖 22

圖3- 1 多晶矽薄膜電晶體之通道調變ID-VG圖 28
圖3- 2多晶矽穿隧式電晶體之通道調變ID-VG圖 28
圖3- 3多晶矽薄膜電晶體不同主動層厚度ID-VG圖(對數座標) 29
圖3- 4多晶矽薄膜電晶體不同主動層厚度ID-VG圖(線性座標) 29
圖3- 5 多晶矽薄膜電晶體不同主動層厚度之NGB[11],[12] 30
圖3- 6 電晶體電阻示意圖 31
圖3- 7多晶矽薄膜電晶體不同主動層厚度之串聯電阻 31
圖3- 8多晶矽薄膜電晶體接面圖[14] 32
圖3- 9主動層厚度1000Å之多晶矽薄膜電晶體變溫ID-VG圖 32
圖3- 10主動層厚度500Å之多晶矽薄膜電晶體變溫ID-VG圖 33
圖3- 11不同主動層厚度之多晶矽薄膜電晶體變溫圖 33
圖3- 12多晶矽穿隧式電晶體不同主動層厚度ID-VG圖(對數座標) 34
圖3- 13多晶矽穿隧式電晶體不同主動層厚度ID-VG圖(線性座標) 34
圖3- 14多晶矽穿隧式電晶體主動層厚度(20nm)能帶圖-開啟狀態[15] 35
圖3- 15多晶矽穿隧式電晶體主動層厚度(100nm)能帶圖-開啟狀態[15] 36
圖3- 16多晶矽穿隧式電晶體關閉狀態ID-VG放大圖 36
圖3- 17不同主動層厚度的多晶矽穿隧式電晶體通道調變效應 37
圖3- 18 主動層厚度1000Å之穿隧式電晶體變溫ID-VG圖 37
圖3- 19主動層厚度500Å之穿隧式電晶體變溫ID-VG圖 38
圖3- 20不同主動層厚度之穿隧式電晶體變溫圖 38

 
表目錄

表3- 1 多晶矽薄膜電晶體不同主動層厚度之電性參數 30
表3- 2多晶矽薄膜電晶體不同主動層厚度之NGB與Nit 30
表3- 3多晶矽穿隧式電晶體不同主動層厚度電性參數 35

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