在本篇論文中我們提出一個新型閘極控制PN感應式穿隧場效應電晶體，其利用源極與閘極間的重疊，大幅增加線穿隧面積，提高元件開啟電流。此線穿隧場效應電晶體善用感應式通道層進而達到更好的次臨界表現，降低能陷輔助穿隧效應及克服雙極性效應。透過利用感應式通道層進行線穿隧的更有效地機制，使感應式穿隧場效應電晶體比傳統PIN穿隧場效應電晶體擁有更好的性能。線穿隧機制在我們的閘極控制PN感應式穿隧場效應電晶體將會有更深入的討論。此外，能陷輔助穿隧效應的影響在我們的元件上也會進一步探討。我們所提出之善用感應式通道層的負型穿隧場效應電晶體(n-iTFET)，在外加偏壓Vd = 0.1 V 下，可達到開啟電流1.46 × 10-7 A/μm且開啟關閉電流比達3.57 × 107，達到了最小次臨界擺幅10.5 mV/dec與從閘極電壓為零(VG = 0)到門檻電壓(VG = Vth)平均次臨界擺幅31.8 mV/dec。當我們對元件加入能陷輔助穿隧，負型感應式穿隧場效電晶體(n-iTFET)擁有平均次臨界擺幅51.8 mV/dec與1.35 × 105的開啟關閉電流比。

In this thesis we proposed a new type Gated-PN iTFET whose source and gate overlap increases the line tunneling area and improve the on current. It is a new mainly line tunneling field transistor exploiting induced channel layer (iTFETs) to achieve better subthreshold performance, reduced trap-assisted tunneling effect and overcome ambipolar effect. Exploiting the more efficient mechanism, line tunneling via induced channel layer, makes the iTFET have the better performance compared with a conventional point tunneling Gated-PIN TFET. The line tunneling mechanism in this Gated-PN iTFET will be discussed in depth. In addition, the impact of the alleviated trap-assisted tunneling on this new-type device will be further studied. Our proposed n-iTFET reaches 1.46 × 10-7 A/μm of the ON current and 3.57 × 107 of the ON/OFF current ratio under Vd = 0.1 V. A minimum subthreshold swing SSmin = 10.5 mV/dec and the SSavg = 31.8 mV/dec are also obtained from VG = 0 to Vth. As the trap-assisted tunneling is considered, the Gated-PN iTFETs still have an average SS = 51.8 mV/dec over four orders and ON/OFF current ratio of 1.35 × 105.

中文審定書 i
英文審定書 ii
致　謝 iii
摘　要 iv
Abstract v
Contents vi
List of Figures viii
List of Tables xii
Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 New Architecture 4
Chapter 2 Device Structure and Fabrication 6
Chapter 3 Device Characteristics 9
3.1 Physical Modeling of Device Simulation 9
3.2 Device Operation Mechanism 10
3.3 Simulation Characteristics 18
3.3.1 Energy Band Diagrams of Point Tunneling and Line Tunneling for Different Structures 18
3.3.2 Gated-PN Tunneling Field Transistor with Exploiting Induced Channel Layer 19
3.3.3 Gated-PN iTFET Dimension Optimization Research 21
3.3.4 Gated-PN iTFET Concentration Modulation Research 23
3.3.5 Discussion on Gated-PN iTFET with Trap-assisted Tunneling 28
3.3.6 Discussion on Gated-PN iTFET with Line Tunneling Enhancement (LTE) Layer 35
3.3.7 Gated-PN iTFET Gate Alignment Discussion 44
3.3.8 Characteristics of Gated-PN iTFET, Gated-PIN iTFET and Traditional TFET 48
3.3.9 Impact of Gox Thickness 52
3.3.10 Inverter and Voltage gain 54
Chapter 4　Conclusion and Future Work 57
4.1 Conclusion 57
4.2 Future Work 59
References 61
Appendix 70

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