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博碩士論文 etd-0715102-173858 詳細資訊
Title page for etd-0715102-173858
論文名稱
Title
選擇性矽鍺汲極源極複晶矽薄膜電晶體之製作與研究
Study of Self-Aligned SiGe Elevated S/D poly-Si Thin-Film Transistor
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
62
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2002-07-05
繳交日期
Date of Submission
2002-07-15
關鍵字
Keywords
薄膜電晶體、矽鍺選擇性沉積
TFT, SiGe selectively raised source/drain
統計
Statistics
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The thesis/dissertation has been browsed 5787 times, has been downloaded 4189 times.
中文摘要
摘要
本論文主要方向在選擇性矽鍺汲極源極複晶矽薄膜電晶體之製作與研究。矽鍺複晶矽薄膜電晶體之汲極與源極部分是由超高真空化學汽相沉積系統在溫度550℃下選擇性沉積矽鍺。如此一來我們的薄膜電晶體就擁有薄的通道部分以及自我對準而且較厚的汲極與源極部分,因而得到較理想的元件特性。與之前傳統複晶矽薄膜電晶體相較下,矽鍺複晶矽薄膜電晶體在輸出特性上明顯的改善導通電流。傳統複晶矽薄膜電晶體在電流特性上,可以清楚地看出電流受限於嚴重的電阻特性。尤其是在閘極電壓加大時,傳統複晶矽薄膜電晶體的電流特性受汲極源極高電阻的影響更為顯著。我們新的複晶矽薄膜電晶體對照於傳統的複晶矽薄膜電晶體,不僅擁有較好的輸出的特性、導通電流比。因為矽鍺汲極源極有效降低汲極端的電場,所以能降低漏電流以及保留該有的汲極崩潰電壓。

Abstract
Abstract
In this thesis, we have fabricated a novel poly-Si thin film transistor with self-aligned SiGe raised source/drain (SiGe-RSD TFT). The SiGe-RSD regions were grown selectively by ultra-high vacuum chemical vapor deposition (UHVCVD) at 550℃. The resultant transistor structure features a thin active channel region and a self-aligned thick source/drain region, which is ideally suited for optimum performance. A significant improvement on the turn-on current in the transfer characteristics is observed, compared to the conventional TFT counterpart. While the conventional TFT depicts severe resistance-limited output characteristics, especially at high gate bias, due to large source and drain series resistance. The new device, in contrast, exhibits excellent output characteristics. Finally, with comparable leakage current in both structures, the on/off current ratio is approximately 2 order of magnitudes higher in the proposed SiGe-RSD TFTS

目次 Table of Contents
Contents

Abstract ( Chinese )
Abstract ( English )
Acknowledgement
Figure Captions
Chapter 1 Introduction…………………………………………………...1
1.1 Overview of polysilicon thin-film transistor ……………………………...1
1.2 Defects in poly-Si film……………………………...……………………..2
1.3 Motivation…………………………………………………………………3
1.4 Thesis Outline……………………………………………………………...4

Chapter 2 Poly-Si films Preparation by LPCVD & UHVCVD… 6
2.1 Introduction……………………………….………………………………6
2.2 The Environment for Depositing Ultra-Thin Film……...………….7
2.3 Poly-SiGe Selectively Deposited by UHVCVD System…………….8
2.4 Description of the UHV/CVD System……………………………….…8

Chapter 3 Fabrication and Measurement of the Novel Ultra-Thin Poly-Si TFT…………………………………………………………………………………..10
3.1 Poly-Si TFT Fabrication Process……………………………………10
3.2 Measurement of Device Parameter…………………………………13
3.2.1 I-V Measurement……………………………………………......13
3.2.2 Measurement of Electrical Parameter…………….................13
3.2.3 Method of Parameter Extraction……………………………….14
3.2.3.1 Determination of Threshold Voltage…………………14
3.2.3.2 Determination of Subthreshold Swing……………….14
3.2.3.3 Determination of Field Effect Mobility……………….15
3.2.3.4 Determination of On/Off Current Ratio……………16
3.2.3.5 Determination of the trap state density………….16

Chapter 4 Results and Discussion…….……………………………………..19
4.1 Transfer Characteristics…………………………………….19
4.2 Source/Drain resistivity…………………………..…...……20
4.3 Breakdown Voltage………………………………………....21
4.4 Device Characteristics after NH3 Plasma………………………22

Chapter 5 Conclusion…….……………………………………………………..23
References…………………………………….….…………………………….25

Figures

參考文獻 References
References
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