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URN	etd-0715104-141351
Author	Peng Tzuhsuan
Author's Email Address	No Public.
Statistics	This thesis had been viewed 4620 times. Download 3884 times.
Department	Electrical Engineering
Year	2003
Semester	2
Degree	Master
Type of Document
Language	English
Title	A Low Jitter High Linearity Voltage Controlled Oscillator
Date of Defense	0000-00-00
Page Count	48
Keyword	High linearity Low jitter VCO Regulator
Abstract	Phase locked loops (PLL) are used in many applications. Application examples include clock and data recovery, clock synthesis, frequency synthesis, modulator, and de-modulator. In many circuits, PLL must provide an output clock to follow the input clock closely. For high speed environments, the noises also rise up. Noises mainly come from the power supply and substrate. They produce jitter. A low jitter design is important in PLL circuit. In this thesis, we discuss the Voltage Controlled Oscillator (VCO) which has the largest jitter in PLL system.   We propose a low jitter voltage controlled oscillator designed in TSMC 0.35μm 2P4M Mixed-Signal process technology. We include a regulator to reduce jitter by increasing the VCO PSRR. This structure also provides a high linearity gain (Kvco) which decreases the VCO jitter in the PLL circuit and improve the system stability.
Advisory Committee	Shyh-Jye Jou - chair Jyi-Tsong Lin - co-chair Yao-Tsung Tsai - co-chair Chia-Hsiung Kao - advisor
Files	etd-0715104-141351.pdf indicate access worldwide
Date of Submission	2004-07-15

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