鎖相迴路電路應用在許多方面。例如時脈訊號的產生與資料回復以及頻率合成器、調頻器、解頻器的應用上。鎖相迴路必須能夠提供緊密跟隨輸入時脈的一個輸出時脈訊號﹔而在高頻環境時，時脈雜訊也隨之增加。雜訊主要的來源在於供應電壓雜訊與基板雜訊。因此在鎖相迴路電路設計中擁有低雜訊抖動是很重要的。在本論文中，我們討論在鎖相迴路系統之中，產生最大雜訊抖動的電壓控制震盪器。

我們提出了一個低抖動的電壓控制震盪器，採用台積電0.35μm 2P4M 混合信號製程完成電路設計。我們在震盪電路中加入穩壓器用來降低供應電壓雜訊，藉此提高整體電路的供應電壓抑制雜訊比。此電路架構提供了一個高度線性的增益(Kvco)，可以降低震盪器雜訊並使得鎖相回路擁有更高的穩定度。

Phase locked loops (PLL) are used in many applications. Application examples include clock and data recovery, clock synthesis, frequency synthesis, modulator, and de-modulator. In many circuits, PLL must provide an output clock to follow the input clock closely. For high speed environments, the noises also rise up. Noises mainly come from the power supply and substrate. They produce jitter. A low jitter design is important in PLL circuit. In this thesis, we discuss the Voltage Controlled Oscillator (VCO) which has the largest jitter in PLL system.

We propose a low jitter voltage controlled oscillator designed in TSMC 0.35μm 2P4M Mixed-Signal process technology. We include a regulator to reduce jitter by increasing the VCO PSRR. This structure also provides a high linearity gain (Kvco) which decreases the VCO jitter in the PLL circuit and improve the system stability.

Abstract
Chapte1. Introduction……………………………………………1
Chapter2.Conventional Oscillators
Section 2.1 L-C Tank Oscillator…………………………2
Section 2.2 Relaxation Oscillator………………………………4
Section 2.3 Ring Oscillator.……………………………………5
Section 2.4 Summary of VCOs …………………………………7

Chapter3.The proposed Voltage Controlled Oscillator………8

Section 3.1 Current Controlled Oscillator……………………9
Section 3.1.1 High Speed Schmitt Trigger……………………10
Section 3.1.2 The CCO Circuit………………………………12
Section 3.2 Voltage-to-Current Converter
Section 3.2.1 Type1 V-I Converter…………………………15
Section 3.2.2 Type2 V-I Converter……………………………17
Section 3.3 Regulator……………………………………………19
Section 3.3.1 Self-Biasing Voltage Reference……………20
Section 3.3.2 Cascode Self-Biasing & voltage divider…23
Section 3.3.3 Voltage Follower & Output Driver…………25
Section 3.4 The Proposed Circuits……………………………28



Chapter4.Results & Discussions

Section 4.1 Design Issues…………………………………………30

Section 4.1.1 Jitter Effect……………………………………30
Section 4.1.2 Jitter Definitions………………………………31
.
(a) The Cycle-to-Cycle Jitter…………………………………31
(b) The Period Jitter…………………………………………32
(c) The Long-Term Jitter……………………………………33

Section 4.1.3 VCO Linearity……………………………………34

Section 4.2 The Frequency Versus Voltage Diagrams………36
Section 4.3 Jitter Simulation and Results…………………38
Section 4.4 Layouts and Measured Results…………………41
Section 4.5 Comparison Lists…………………………………45


Chapter5.Conclusion……………………………………………46

Reference…………………………………………………………47

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