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博碩士論文 etd-0715113-130236 詳細資訊
Title page for etd-0715113-130236
論文名稱
Title
運用於橢圓曲線密碼系統之高效能蒙哥馬利點乘演算法硬體架構
High-Performance Hardware Architecture of Montgomery Point Multiplication Algorithm for Elliptic Curve Cryptosystem
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
68
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2013-07-24
繳交日期
Date of Submission
2013-08-19
關鍵字
Keywords
串鍊、迴圈折疊、有限場乘法器、蒙哥馬利點乘演算法、多項式基底、不可約分多項式、超大型積體電路設計、特殊用途積體電路設計、字組式乘法器、橢圓曲線密碼系統
digit-serial multiplier, irreducible polynomial, polynomial basis, Montgomery Point Multiplication Algorithm, Elliptic Curve Cryptosystem, ASIC design, VLSI, finite field multiplier, loop folding, loop chaining
統計
Statistics
本論文已被瀏覽 5660 次,被下載 296
The thesis/dissertation has been browsed 5660 times, has been downloaded 296 times.
中文摘要
公開金鑰密碼系統(非對稱式密碼系統)是密碼學中的一種協定方式, RSA (Rivest-Shamir-Adleman )與橢圓曲線密碼學(Elliptic Curve Cryptography)可說是其中典型的代表。而橢圓曲線密碼系統的優勢除了在求解橢圓曲線離散對數上具有全指數性的時間複雜度外,其160 位元的金鑰長度就可以達到等同於RSA 1024位元的安全性,且加解密的速度更快,故成為近年來相當熱門的研究領域。
本論文基於蒙哥馬利點乘演算法(Montgomery Point Multiplication Algorithm)及其基礎硬體演算法,利用算術單元串鍊(Arithmetic Unit Chaining)與迴圈折疊(Loop Folding)的技巧提出新型的硬體演算法排程,以彌補因為低面積與低功耗導向而降低乘法器的效能後,所造成之整體點乘效能的犧牲。其中倒數部分以Itoh-Tsujii演算法為基礎,設計八級平方器串接之ITMIA倒數加速電路架構。此外,本論文也針對4種字組大小的字組式乘法器(digital-serial)進行面積與效能上的比較並修改其架構,再分別套用至所提出的兩種改良式硬體排程中加以實現。
在硬體實作部分,我們使用國家實驗研究院晶片系統設計中心(以下簡稱CIC)所提供的TSMC 0.13 μm CMOS製程進行邏輯合成。實驗結果顯示,在相同金鑰長度(key length, or field size)與相同工作速度下,本論文提出的改良式演算法排程,相較於比較數據可降低近20%的面積,其低面積複雜度的特性,非常適合使用於現代橢圓曲線密碼系統硬體加速電路與行動裝置上。
Abstract
The public key cryptosystem (asymmetric cryptography system) is an agreement in cryptography, and RSA (Rivest - Shamir - Adleman) and elliptic curve cryptography (ECC) are the typical representative. The advantages of Elliptic Curve Cryptography contain that the elliptic curve discrete logarithmic is solved in exponential time complexity, 160-bit key length can achieved the security of the 1024-bit RSA, there is fast decryption thus ECC has become very popular research field in recent years.
Based on the Montgomery point multiplication algorithm and its hardware architecture, this thesis uses loop chaining and loop folding skills to obtain new schedules of hardware algorithms so that can be enhanced while maintaining the multiplier performance overall point multiplication performance by low area and low power. Moreover we use the design the eight series square circuit ITMIA architecture for the inversion circuit based on Itoh-Tsujii algorithms. In addition, we also compare the area and performance of the different word-base (digital-serial) multipliers and then apply loop chaining and loop folding to them, leading to more efficient schedules and hardware architecture.
Finally, we use TSMC 0.13μm CMOS process provided by CIC is used to synthesis the proposed architecture. Comparing to the arithmetic unit (Arithmetic-Unit) scheduling methods proposed in other references, experimental results show that improved algorithm schedule proposed by this thesis achieve 20% area performance in the same operation speed and irreducible polynomial basis. The low area complexity characteristic is ideally suited for mobile communication systems, mobile devices and modern elliptic curve cryptosystem.
目次 Table of Contents
論文審定書 ............................................................................................................................... i
論文提要 ............................................................................................................................... ii
誌謝 ............................................................................................................................... iii
中文摘要 ............................................................................................................................... iv
Abstract ............................................................................................................................... v
目錄 ............................................................................................................................... vii
圖目錄 ............................................................................................................................... ix
表目錄 ............................................................................................................................... x
第一章 緒論 ............................................................................................................................... 1
1.1研究動機 ............................................................................................................................... 1
1.2論文大綱 ............................................................................................................................... 2
第二章 研究背景 ............................................................................................................................... 3
2.1密碼系統簡介 ............................................................................................................................... 3
2.2橢圓曲線密碼系統概述 ............................................................................................................................... 4
2.2.1橢圓曲線數學背景概述 ............................................................................................................................... 4
2.2.2仿射座標(Affine Coordinate)系統 ............................................................................................................................... 7
2.2.3射影座標(Projective Coordinate)系統 ............................................................................................................................... 9
2.2.4點乘演算法(Point Multiplication) ............................................................................................................................... 10
2.2.5有限場基底的基本介紹 ............................................................................................................................... 12
2.2.6二元體有限場下橢圓曲線點乘的整體架構 ............................................................................................................................... 12
第三章 有限場模數多項式算術與硬體實現 ............................................................................................................................... 14
3.1多項式加法運算 ............................................................................................................................... 14
3.2多項式乘法運算 ............................................................................................................................... 15
3.2.1餘式化簡(Modular Reduction) ............................................................................................................................... 16
3.2.2序列(Bit-Serial)乘法器架構 ............................................................................................................................... 17
3.2.3平行(Bit-Parallel)乘法器架構 ............................................................................................................................... 17
3.2.4字組式(Digit-Serial)乘法器架構 ............................................................................................................................... 19
3.2.5乘法器架構小結 ............................................................................................................................... 25
3.3多項式平方運算 ............................................................................................................................... 26
3.4多項式倒數運算 ............................................................................................................................... 28
第四章 蒙哥馬利點乘演算法之改進 ............................................................................................................................... 32
4.1蒙哥馬利點乘演算法平行化硬體架構 ............................................................................................................................... 34
4.2減少一個時脈週期的排程 ............................................................................................................................... 36
4.3算術單元串鍊設計(Arithmetic Unit Chaining) ............................................................................................................................... 38
4.4三乘法器之迴圈折疊設計(Loop Foling) ............................................................................................................................... 41
4.5座標軸轉換與效能評估 ............................................................................................................................... 44
第五章 硬體驗證與實驗數據 ............................................................................................................................... 45
5.1實作驗證 ............................................................................................................................... 45
5.2實驗數據分析 ............................................................................................................................... 49
第六章 結論與未來研究方向 ............................................................................................................................... 53
6.1結論 ............................................................................................................................... 53
6.2未來研究方向 ............................................................................................................................... 53
參考文獻 ............................................................................................................................... 54
參考文獻 References
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