現今的ARM program debug都是需要藉由ARM開發的RVDS [18] (RealView Development Suite)以及MULTI-ICE (protocol converter)環境以控制ICE控制CPU，來達到對程式的偵錯，現在我們有新的選擇，就是Eclipse、GDB與OpenOCD (Open On-Chip Debugger)所組合起來的debug tool chain，配合FIDI公司出品的protocol converter型號為ft2232進行程式的偵錯。

然而對於本身實驗室有開發ARM7-like的CPU，即SYS32TM，與可控制CPU的ICE模組，不管是ARM本身開發的RVDS或者OpenOCD都無法可以簡單的看到debugger與ICE的互動，造成不管是為了驗證ICE或OpenOCD的正確性都非常的難，為了解決此問題我們思考了，使用PLI(Program Level Interface)與RTL simulator溝通再連接OpenOCD，或使用Platform Architect本身的co-simulation環境連接OpenOCD，最後決定採用Platform Architect環境，並找到embecosm EAN5裡面的JTAGSC [3]當成protocol converter 放入Platform Architect環境，並藉由shared memory機制與OpenOCD溝通已達到協同驗證的目的。

We usually use RVDS [18] (RealView Development Suite) and MUlTI-ICE (protocol converter) as ARM program debug environment by controlling ICE module for controlling CPU. But now we have another choice, ie the debug tool chain that Eclipse, GDB and OpenOCD (Open On-Chip Debugger) combination. We achieve program debugging by using a protocol converter called ft2232 that FIDI Company produced to connect ICE module with JTAG port.

However, for ARM7-like CPU, ie. SYS32TM, ICE can control the CPU module that our laboratory develops. No matter the ARM RVDS or OpenOCD can not observate the interactive of debugger and ICE, it such that the verification of ICE and debugger is a difficult thing. In order to solve this problem, we consider PLI (Program Level Interface) to communicate with the RTL simulator and then connect to OpenOCD, or use the Platform Architect itself co-simulation environment connected OpenOCD. Finally, we chose Platform Architect environment and find the JTAGSC [4] as a protocol converter that come from embecosm EAN5 that can put into the Platform Architect environment. To achieve the purpose of co-verification, we ued shared memory mechanism to communication with OpenOCD and Platform Architect environment that JTAGSC had put into.

Chapter 1 簡介 1
1.1 背景 1
1.2 動機 2
1.3 提出的解法 3
1.4 本研究貢獻 4
Chapter 2 相關技術與文獻 6
2.1 雛型階段應用程式除錯方法 8
2.1.1 目標監督程式 8
2.1.2 邏輯分析儀 8
2.1.3 電路擬真器（In Circuit Emulator） 9
2.2 嵌入式系統應用程式除錯架構 10
2.2.1 即時追蹤除錯器 10
2.2.2 嵌入式電路擬真器 11
 JTAG 架構 13
 嵌入式電路擬真器 15
2.3 用於控制電路擬真器之除錯器 17
2.3.1 Open On-Chip Debugger [2] 18
2.3.2 GDB [6] 20
2.4 SC-RTL 協同模擬平台 21
Chapter 3 SYS32TM-OpenOCD 協同驗證平台 22
3.1 協同驗證平台開發動機 22
3.2 協同驗證平台研究方法 25
3.3 OpenOCD與JTAGSC如何連接 27
3.3.1 基於共享記憶體技術的溝通機制 28
3.3.2 補足JTAGSC不足之處的修改 30
3.3.3 OpenOCD新增JTAGSC驅動程式與初始化流程修改 33
3.3.4 協同驗證平台總觀 39
3.4 協同驗證平台如何重複利用 39
3.4.1 SC-RTL 協同模擬平台內部用到的元件與接線說明 40
3.4.2 如何使用協同驗證平台 43
Chapter 4 實驗 47
4.1 SC model (JTAGSC)和RTL model (SYS32TM+EICE) 可以正常執行協同模擬 47
4.2 OpenOCD與SC+RTL model互動驗證 49
4.3 GDB 需要EICE幫助的除錯動作 51
4.4 Semihosting 機制 60
4.5 在協同驗證平台執行應用程式除錯範例 62
4.6 實際範例-以JPEG編碼程式與3DG SoC程式為例 72
4.6.1 JPEG 編碼程式 72
4.6.2 3D graphs SoC 應用程式 78
Chapter 5 結論與未來發展 81
Appendix A OpenOCD 架構 84
A.1 OpenOCD 架構與運作流程 84
A.1.1 OpenOCD內部模組 84
A.1.2 OpenOCD 初始化與運作流程 86
A.1.2.1 OpenOCD 初始化流程 86
A.1.2.2 OpenOCD 運作流程 87
A.2 ITRI’s Project – PACDUO（高效能平行架構核心採用ARM9以及雙DSP為發展平台） 88
A.2.1 PACDUO [15] 88
A.2.2 PACDUO除錯效能與使用GDB控制問題 90
A.2.3 尋找PACDUO 問題所使用的方法 90
A.2.4 PACDUO問題解決與最後結果 92
Appendix B EICE_control_event/JTAG 轉換器說明 95
B.1 JTAGSC 介紹 95
B.2 JTAGSC檔案目錄列表與編成元件可在SC-RTL協同模擬平台使用 97
B.2.1 JTAGSC 檔案目錄與結構 97
B2.2 JTAGSC如何可以被當成元件在SC-RTL協同模擬平台上使用 98
B.3 JTAGSC運作流程 99
B.3.1 JtagSC.cpp and JtagSC.h 100
B.3.2 JTAGSC API運作流程 104
B.3.3 TapStateMachine 106
Appendix C 藉由協同驗證平台所找到的OpenOCD與EICE錯誤 108
C.1 SYS32TM 無法被停止 108
C.2 EICE無法控制SYS32TM寫入記憶體 110
C.3 中斷點觸發之後停止的位址不是設定中斷點得位址 112

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