無線通訊系統的資料在空氣中傳播時容易受到雜訊干擾而失真，所以在傳送端通常會使用迴旋編碼(Convolution code)將資料進行編碼，經由通道傳送後，接收端則採用維特比解碼器(Viterbi decoder)將收到的資料解碼。維特比解碼器是利用維特比演算法(Viterbi Algorithm)找出最大相似解進行解碼並且更正錯誤位元，在目前行動通訊中，基地台和通訊裝置間經常使用這種解碼器當作解碼的機制。由於傳統解碼器所消耗的功率佔整個訊號接收器的三分之一以上，因此如何有效降低維特比解碼器的功率消耗，成為本論文研究的重點。在維特比解碼器中，存活記憶體單元使用大量記憶元件記憶每個狀態的路徑，在收到足夠長的迴旋碼後路徑會漸漸收斂，然後再解碼輸出，因此存活記憶體單元消耗很大的功率，故本論文著重於降低此單元的功率消耗。本論文是以追溯法來進行解碼，追溯法的三個基本動作分別為：寫入決策位元、追溯讀出和解碼輸出。為了降低存活記憶體的功率消耗，我們額外加入預先追溯電路，預先追溯電路可以在存活記憶體寫入決策位元的同時，就利用指標暫存器進行預先追溯，使存活記憶體單元內不再需要追溯讀出的動作，如此一來可以讓存活記憶體單元電路面積下降並花費較小的延遲時間解得資料，還能降低整體電路的功率消耗。此外，本論文也結合了錯誤偵測的概念，在收到的迴旋碼進入維特比解碼器之前，可以將迴旋編碼中受到雜訊干擾的片段標記並利用維特比解碼器解碼，沒有受到雜訊干擾的片段則利用功率消耗較低的簡單解碼器解碼，更進一步降低功率消耗。

In wireless communication system, the data will be interfered easily with noise during transmission, thus the transmitter usually uses convolution code to encode the data. The receiver usually utilizes Viterbi decoder to decode the data which received from the channel. Viterbi decoder is based on Viterbi algorithm, and it can be used to decode and correct the data. In mobile communication, Viterbi decoder is often used between the cell site and the communication device as a decoding mechanism. Because the traditional decoder consumes more than one-third power in the receiver, we focus on how to reduce the power consumption of Viterbi decoder.
The survivor memory unit (SMU) needs a lot of memory units to keep the path of states in Viterbi decoder so that it will consume large amounts of power. The goal of this thesis is to reduce the power consumption of SMU. In this thesis, SMU uses traceback method to decode the data. Traditional traceback is based on three kinds of memory operations: decision bit write (WR), traceback read (TB), decode read (DC). In order to reduce the power consumption of SMU, the pre-traceback unit is used. Pre-traceback unit utilizes pointer register for pre-traceback operation, and it can operate as soon as SMU writes the decision bits. SMU doesn’t need TB operation anymore so that the area ,latency and power consumption of SMU will be reduced .

論文審定書………………………………………………………………………………………………………………i
論文提要…………………………………………………………………………………………………………………ii
誌謝………………………………………………………………………………………………………………………iii
摘要………………………………………………………….…………………………………………………………..iv
Abstract....……………………………………..…………………….……………….………………………………...v
第一章 緒論1
1.1 研究背景1
1.2 研究動機與方向3
1.3 論文組織4
第二章 相關研究與背景知識5
2.1 迴旋碼5
2.1.1 迴旋碼(Convolution Code)簡介5
2.1.2 迴旋碼架構6
2.1.3 去尾迴旋碼(Tail-biting Convolution Code)簡介9
2.2 維特比演算法與架構12
2.2.1 維特比演算法12
2.2.2 維特比解碼範例16
2.2.3 暫存器交換法18
2.2.4 追溯法19
2.2.5 WAVA演算法20
第三章 迴旋碼之錯誤偵測22
第四章 硬體架構24
4.1 維特比解碼器硬體架構設計24
4.2 存活記憶體硬體設計與改善27
4.2.1 存活記憶體追溯策略27
4.2.2 追溯法之存活記憶體管理29
4.3 預先追溯法31
4.3.1 預先追溯(Pre-traceback)演算法31
4.3.2 利用預先追溯法改良存活記憶體內記憶體區塊35
4.3.3 指標暫存器架構設計36
4.4 錯誤偵測電路架構39
第五章 驗證與實驗數據44
5.1 Matlab模擬雜訊通道44
5.2 矽智產驗證46
5.3 雜訊分析46
5.4 實驗數據47
第六章 結論與未來工作57
參考文獻59

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