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博碩士論文 etd-0715117-151732 詳細資訊
Title page for etd-0715117-151732
論文名稱
Title
運用於低偏壓高速度操作之兩種無摻雜橋的單電晶體動態隨機存取記憶體
Two Doping Less Bridge Single-Transistor DRAMs for Low-Power Supply and High-Speed Application
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
105
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2017-07-27
繳交日期
Date of Submission
2017-08-21
關鍵字
Keywords
抬高本體架構、單電晶體動態隨機存取記憶體、無摻雜橋、垂直式元件、低偏壓操作、快速操作
Low Power Supply, Fast Operation, Vertical Device, 1T-DRAM, Dopingless Bridge, Raised Body Structure
統計
Statistics
本論文已被瀏覽 5644 次,被下載 17
The thesis/dissertation has been browsed 5644 times, has been downloaded 17 times.
中文摘要
本論文中,我們提出兩種運用無摻雜橋的無電容式單電晶體動態隨機存取記憶體(Single-Transistor Dynamic Random Access Memory, 1T-DRAM)之架構。這也是第一次以無摻雜橋做為1T-DRAM讀取橋時所採用的技術。
第一種架構稱之無摻雜橋的單電晶體動態隨機存取記憶體(Dopingless Bridge Single-Transistor Dynamic Random Access Memory, DLB 1T-DRAM)。在儲存區部分我們採取抬高式本體此架構能在不佔用額外面積下增加其儲存區大小,進而增加過量載子儲存量。並可以使儲存之過量載子遠離讀取時產生複合及P-N接面複合的影響,達到延長儲存時間效果。在DRAM最耗能的寫入動作時並在相同架構及偏壓比較下,無摻雜橋模式比N+型電流橋模式節省約44.2%之功率消耗,並可低於2奈秒的快速寫入能力。另在可程式編程視窗為39.74 μA/μm,並有著超過100毫秒的資料保存時間。在操作偏壓上更可應用在1.0伏特的低偏壓操作。
第二種是垂直式無摻雜橋的單電晶體動態隨機存取記憶體(VDLB 1T-DRAM)。可以減少第一種架構讀取動作時的複合負面影響、Middle Oxide無自我對準能力。垂直方向可減少元件佔據晶圓面積且垂直式元件也是近年元件發展方向,減少線寬技術限制。此架構下的可程式編程視窗為31.2 µA/ µm,常溫下資料保存時間達800毫秒,高溫操作下為63.8毫秒。寫入時間不受橋濃度影響,在元件穩定度上減少了一種變異性的存在。在功率消耗方面,採用無摻雜橋比N型電流橋節省約52.4%。另外,元件的操作電壓不超過1.2伏特且可達2奈秒的快速寫入能力。
Abstract
In this thesis, we propose two architectures of Single-Transistor Dynamic Random Access Memory (1T-DRAM) using dopingless bridge. This is also the first time using the Dopingless Bridge as 1T-DRAM reading current channel.
The first architecture is called Dopingless Bridge Single-Transistor Dynamic Random Access Memory (DLB DRAM). We utilize Raised body in the storing region. It can increase the size of storing area without occupying additional area, thus increasing storing excess carriers. It also let storing carriers far away from the recombination of reading and PN junctions to extend the retention time. Writing operation needs the most power while DRAM is working. At writing operation, Dopingless Bridge mode saves about 44.2% of the power consumption compared to the N-type current bridge mode under the same architecture and bias. Its write time can less than 2 ns. On the performance of programming window is 39.74 μA/μm and performance of retention time can over than 100 ms. The device even can be applied at low power supply operation of 1.0 V.
The second device is Vertical Dopingless Bridge Single-Transistor Dynamic Random Access Memory (VDLB 1T-DRAM). It can decrease the recombination while reading operation and avoid the problem of middle oxide self-alignment in DLB 1T-DRAM. The vertical direction of channel can reduce the area occupied by device on the wafer. It also is the trend of developing device in recent years. The performance of programming window is 31.2 μA/μm. The performance of retention time reach 800 ms at room temperature 300 K and 63.8 ms at 358 K.The writing time is not affected by the channel concentration and reduces on of the variability in device stability. Compared to the N-type current bridge, using of Dopingless Bridge reduces about 52.4% power consumption in this device. In addition, the operating voltage is less than 1.2 V and has 2 ns fast write time.
目次 Table of Contents
中文審定書 i
英文審定書 ii
致謝 iii
摘 要 iv
Abstract v
目 錄 vi
圖 次 viii
表 次 xii
第一章 導 論 1
1.1 研究背景 1
1.2 動機 4
第二章 元件操作機制設計 6
2.1無電容式單電晶體動態隨機存取記憶體操作機制說明 6
第三章 元件製作 12
3.1元件模擬製程 12
第四章 DLB 1T-DRAM元件之研究方法探討及結果討論 14
4.1 物理機制模型探討 14
4.2 無摻雜橋概念運用探討 16
4.3 DLB 1T-DRAM元件操作說明 20
4.4 DLB 1T-DRAM元件之記憶體特性探討 21
4.5 DLB 1T-DRAM元件之電性討論 47
4.6 DLB 1T-DRAM元件之記憶體邊際比較 49
第五章 VDLB 1T-DRAM元件之研究方法探討及結果討論 52
5.1物理機制模型探討 52
5.2 VDLB 1T-DRAM元件架構及操作說明 55
5.3 VDLB 1T-DRAM元件之記憶體特性探討 58
5.4 VDLB 1T-DRAM元件之電性討論 75
5.5 VDLB 1T-DRAM元件之記憶體邊際比較 77
5.6 元件量測 79
第六章 結論與未來展望 82
6.1 結論 82
6.2未來展望 83
參考文獻 84
附錄 91
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