近年來，由於穿隧式薄膜電晶體具有特殊的傳導機制，相較於傳統薄膜電晶體展現出較佳的短通道效應抑制力，因此被廣泛的研究，然而根據目前的文獻，大多數主要是探討如何改善多晶矽穿隧式薄膜電晶體的性能，例如應用不同的結晶法、摻雜活化法、電漿鈍化缺陷…等等，比較少有關於多晶矽穿隧式薄膜電晶體的可靠度研究。
在本論文中，我們透過各個端點施加偏壓應力，發現對傳統薄膜電晶體和穿隧式薄膜電晶體來說，負偏壓應力(NBS)相較於正偏壓應力(PBS)對元件電性的劣化程度皆較為嚴重，這是由於在NBS下產生較多的晶粒邊界陷阱能態(NGB)與界面陷阱能態(Nit)，因此導致元件電性的劣化較為嚴重。
而我們進一步研究發現穿隧式薄膜電晶體在PBS和NBS下的劣化是由源極端的損傷所致，推測是因為穿隧式薄膜電晶體的傳導機制是由源極端穿隧主導，因此汲極端的陷阱產生對電性的影響並不顯著，而源極端的陷阱產生強烈影響元件電性。
在熱載子應力(HCS)量測中，穿隧式薄膜電晶體與傳統薄膜電晶體展現出不同的行為，由於汲極端的損傷對穿隧式薄膜電晶體的電性影響並不顯著，而VD的增加同時提高了通道的電位，使得源極端的垂直電場減弱，減少了源極端的損傷，導致穿隧式薄膜電晶體在相同VG偏壓應力下，隨著VD的增加，元件的劣化程度減緩。

Tunneling thin-film transistor exhibits better short channel effect (SCE) immunity than conventional thin-film transistor due to its special carrier transport mechanism: interband tunneling. According to the current literature, most of them mainly discuss how to improve the performance of poly-silicon tunneling thin-film transistors, such as the application of different crystallization methods, dopant activation methods, plasma passivation defects, etc. However, the reliability of poly-silicon tunneling thin-film transistors is rarely studied.
In this thesis, we apply bias stress through gate, drain, and source, respectively. It is found that for conventional thin-film transistors and tunneling thin-film transistors, the negative bias stress (NBS) is more serious than the positive bias stress (PBS) on the degradation of the devices. Because more grain boundary trap energy states (NGB) and interface trap energy states (Nit) are generated under NBS, the electrical performance degradation of devices is more serious.
Further more, research has found that the degradation of tunneling thin-film transistors under PBS and NBS is caused by the damage of the area near the source, because the conduction mechanism of tunneling thin-film transistors is dominated by source tunneling. Therefore, the damage of the area near the drain has no significant effect on the electrical properties of the devices, while the damage of the area near the source strongly affects the electrical properties of the devices.
In the hot carrier stress (HCS) measurement, the tunneling thin-film transistor exhibits different behavior from the conventional thin-film transistor. Under the same gate stress bias, the degradation of the device is slowed down with the increasing drain stress bias. This is because the damage of the area near the drain has no significant effect on the electrical properties of the tunneling thin-film transistor, and the higher drain stress bias increases the potential barrier of the channel, which weakens the vertical electric field at the area near the source and reduces the damage of the area near the source.

論文審定書 ................................ ................................ ................................ ....................... i
論文公開授權書 ................................ ................................ ................................ .............. ii
誌謝 ................................ ................................ ................................ ................................ . iii
摘要 ................................ ................................ ................................ ................................ . iv
Abstract ................................ ................................ ................................ ............................. v
目錄 ................................ ................................ ................................ ................................ . vi
圖目錄 ................................ ................................ ................................ ........................... viii
表目錄 ................................ ................................ ................................ ............................. xi
第 1章 緒論 ................................ ................................ ................................ .................... 1
1.1 前言 ................................ ................................ ................................ .................. 1
1.2 多晶矽薄膜電體 (Poly-Si Thin-Film Transistor, TFT) ................................ 1
1.3 短通道效應 (Short Channel Effect, SCE) ................................ ........................ 2
1.3.1 汲極導致能障降低(Drain-Induced Barrier Lowering, DIBL) .................... 2
1.3.2 擊穿崩潰 (Punch Through) ................................ ................................ ........... 3
1.4 穿隧式場效電晶體(Tunneling Field-Effect Transistor, TFET) ...................... 3
1.5 穿隧式場效電晶體載子傳輸機制 ................................ ................................ .. 4
1.5.1 產生與複合電流 (Generation and Recombination Current) ........................ 4
1.5.2 陷阱輔助穿隧(Trap-Assisted Tunneling, TAT) ................................ .......... 4
1.5.3 能帶間穿隧(Band-to-Band Tunneling, BTBT) ................................ ........... 5
1.6 薄膜電晶體之可靠度機制 ................................ ................................ .............. 5
1.6.1 正偏壓應力(Positive Bias Stress, PBS) ................................ ....................... 5
1.6.2 負偏壓應力(Negative Bias Stress, NBS) ................................ ..................... 6
1.6.3 熱載子應力(Hot Carrier Stress, HCS) ................................ ......................... 6
1.7 實驗動機 ................................ ................................ ................................ .......... 6
第 2章 實驗步驟與流程 ................................ ................................ .............................. 14
2.1 元件製作 ................................ ................................ ................................ ........ 14
2.2 元件電性參數萃取 ................................ ................................ ........................ 15
2.2.1 臨界電壓(Threshold Voltage, Vth) ................................ ............................. 15
2.2.2 次臨界擺幅(Subthreshold Swing, S.S.) ................................ ..................... 15
2.2.3 開啟電流(On-State Current, Ion) ................................ ................................ 16
2.2.4 關閉電流(Off-state Current, Ioff) ................................ ................................ 16
2.2.5 界面陷阱能態(Interface Trap State, Nit) ................................ ................... 16
2.2.6 晶粒邊界陷阱能態(Grain Boundary Trap State, NGB) ............................. 16
第 3章 結果與討論 ................................ ................................ ................................ ...... 23
3.1 可靠度量測條件 ................................ ................................ ............................ 23
3.2 參數萃取 ................................ ................................ ................................ ........ 23
3.3 傳統薄膜電晶體與穿隧式薄膜電晶體之PBS與NBS .............................. 24
3.4 穿隧式薄膜電晶體之VD Stress ................................ ................................ .... 24
3.5 穿隧式薄膜電晶體之VS Stress ................................ ................................ .... 25
3.6 傳統薄膜電晶體與穿隧式薄膜電晶體之HCS ................................ ........... 26
第 4章 結論與未來展望 ................................ ................................ .............................. 45
參考文獻 ................................ ................................ ................................ ........................ 46

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