在此論文裡，我們成功地製作與研究不同的通道長度與寬度的複晶矽薄膜電晶體。最特別的是我們利用了T型閘極結構與基底接觸電極量測到基底電流與電壓。因此，我們能更清楚研究發生在複晶矽薄膜電晶體裡的短通道效應。為了能夠仔細的研究碰撞游離效應與浮動基底效應，我們量測與比較了不同結晶界面的缺陷密度、晶粒大小與不同的通道尺寸的元件特性。這些因素對於短通道效應的影響也會在論文裡討論與解釋。
在本實驗裡，我們發現通道長度較短的元件有較好的驅動電流與較小的起始電壓。但在另一方面也觀察到由於碰撞游離效應所造成的kink現象。此外，由於薄膜電晶體是製作在玻璃基板上，就如同在製作在矽覆蓋絕緣層結構基板上的元件一樣，由於在通道下的矽基底中會有電洞累積，最後會造成寄生雙接面電晶體現象。在本論文研究裡，在量測短通道元件時我們觀察到相似於單電子元件的閉鎖現象發生，在此也對於此現象對不同的通道寬度來作討論。
為了研究與分析複晶矽薄膜電晶體下嚴重的碰撞游離效應所造成的元件特性。我們在傳統的薄膜電晶體的基底製作了接觸電極，可直接量測到基底的電流，藉此可更清楚地分析碰撞游離效應。此外元件在較大的閘極電壓操作下，我們可觀察到異常的基底電流。此現象是由於閘極下的反轉層與基底所發生的寄生穿隧效應所造成的。最後，我們提出了一個有物理依據的電流模型與實際量測到的基底電流作一個比較。最後我們考慮了垂直電場的散射現象，將此加入到我們的模型裡即可以得到與實驗數據更一致的高電場之碰撞游離模型。

In this thesis, the poly-Si TFTs with different channel width and channel length are successfully fabricated and characterized. In particular, by using the T-gate structure and body contact, we can measure the substrate current and body voltage. Therefore, short channel effects in polycrystalline silicon thin-film transistors are investigated clearly. In order to study impact ionization effect and floating body effect more carefully, we measure and compare the electrical behaviors of device with different grain boundary trap density, grain size, and channel dimension. The influences of these factors on the short channel effects are also discussed and explained.
In this experiment, it is found that the devices with short channel length, exhibit improved normalized turn on current and smaller threshold voltage. But on the other hand the sever kink effect which generated by the impact ionization also observed. Moreover, the floating body under the channel region serve as a parasitic BJT as in silicon-on-insulator devices. The related single transistor latch-up is observed and discussed for short-channel devices with various channel width.
The severe impact ionization effects in polycrystalline silicon thin-film transistors are investigated and characterized. By directly measuring the substrate current from conventional TFTs with body contact, the impact-ionization effects can be characterized and analyzed very clearly. An anomalous substrate current under high gate voltage is observed. The parasitic tunneling effect between inversion region and body region is proposed to explain this phenomenon. Finally, a physically-based model is established and compared with the measured substrate current. Good agreements are found when the vertical field scattering effect is included into the maximum electric field impact ionization model.

Chinese Abstract I
English Abstract III
Contents V
Figure Captions VI
Chapter 1. Introduction 1
1-1. Overview of polysilicon thin-film transistor technology 1
1-2. Defects in ploy-Si film 3
1-3. The influences of grain structure on carrier transport 3
1-4. Motivation 6
1-5. Thesis outline 7
Chapter 2. Fabrication and Characterization 9
2-1. Device fabrication 9
2-2. Method of Device Parameter Extraction 11
2-2-1. Determination of the threshold voltage 11
2-2-2. Determination of the subthreshold swing 12
2-2-3. Determination of On/Off Current Ratio 12
2-2-4. Determination of the field-effect mobility 13
2-2-5. Determination of the trap density 13
2-2-6. Determination of the channel resistance and the parasitic resistance 14
2-3. Device characteristics and short channel effects 15
2-4. Characterization of the substrate current 17
Chapter 3. Unified Impact Ionization Model 20
3-1. The horizontal electric field model 20
3-2. The parasitic tunneling effect 21
3-3. Unified impact ionization model 22
3-4. Physical meanings of the extracted parameters 24
Chapter 4. Conclusions 25
References 26
Figures 32

Chapter 1
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Chapter2
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Chapter3
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