本論文的第一部份提出一個應用標準CMOS製程之一次可燒錄唯讀記憶體，本設計提出利用標準CMOS製程，實現出一次寫入唯讀記憶體(OTP)。燒錄的方法是利用高電壓使閘極氧化層崩潰，造成電阻值的不同，並以此判斷內儲資料之二進位值。
第二部分則為直接數位頻率合成器實作，在此我們提出一種直接數位頻率合成器的設計，利用直線逼近1/4弦波的演算法，並且用查表法作補償，以節省製作成本又兼顧精準度，並利用第一部份所提出的一次可燒錄之唯讀記憶體，簡化查表法的製作並方便製作後的校正及微調。

The first topic of this thesis presents a one-time programmable (OTP) ROM using a standard logic CMOS process. A high voltage is applied to the gate-oxide to breakdown the MOS in the ROM-cell. It results in a low resistance compared to that of unprogrammed cells. Therefore, we can realize an OTP ROM with this characteristic on a CMOS logic ASIC or SOC.
The second topic is a DDFS (Direct Digital Frequency Synthesizer) implementation. A straight-line approximation algorithm for sinusoid with compensation is adopted in the proposed DDFS such that the accuracy could be maintained and the cost is reduced. Most important of all, the proposed CMOS OTP ROM is employed as the sinusoidal look-up ROM table to simplify the ROM fabrication without any additional process step.

摘要 i
Abstract ii
目錄 iii
圖目錄 v
表目錄 viii
第一章 概論 1
1.1 前言 1
1.2 文獻探討 2
1.3 論文大綱 3
第二章 應用標準CMOS製程之一次可燒錄唯讀記憶體 4
2.1 簡介 4
2.2 OTP ROM記憶單元電路與分析 5
2.3 整體OTP電路測試架構 9
2.3.1 記憶單元區塊電路 10
2.3.2 解碼器電路 11
2.3.3 感測放大器電路 12
2.3.4 輸出入控制電路 14
2.4 模擬結果 15
2.4.1 測試區塊電路模擬 15
2.4.2 解碼器電路模擬 16
2.4.3 感測放大器電路模擬 17
2.4.4 預計規格 20
2.5 佈局圖 20
2.6 晶片量測 22
2.6.1 測試區塊量測結果 22
2.6.2 記憶單元區塊量測結果 24
2.7 結論與討論 26
第三章 直接數位頻率合成器實作 30
3.1 簡介 30
3.2 電路架構與原理說明 30
3.2.1 直接數位頻率合成器電路 37
3.2.2 利用唯讀記憶體實現之低位元補償電路 40
3.3 模擬結果 42
3.3.1 數位部份模擬 42
3.3.2 類比部份模擬 43
3.3.3 整合模擬 43
3.3.4 預計規格列表 45
3.4 佈局圖與規格比較 45
第四章 結論與成果 47
4.1 結論與成果 47
4.2 未來展望 48
參考文獻 50

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