本論文提出一個可以產生符合IEEE-754單精度浮點數標準的多重精確度函數插補器產生器與多重精確度浮點乘加器產生器，使用者可以依需求選擇產生具有多重精確度的硬體架構。函數插補器可以執行倒數、倒數開根號、對數與指數運算，浮點乘加器可以執行乘法、加法與乘累加法運算，每種運算可以使用不同精確度模式運算。其硬體架構以管線化方式設計，以符合數位訊號處理器(DSP)、圖形處理器(GPU)之硬體架構特性。
函數插補器是基於查表法所設計，透過運算二次多項式求得目標函數的近似值，其中二次多項式的係數是採用多區間極大極小近似法求得。浮點乘加器將浮點乘法和浮點加法組合為一個單元執行乘累加，當乘法運算時，加法的小數點對齊動作也會平行運算。多重精確度函數插補器與浮點乘加器乘法運算除了最高精確度模式外，可以根據部分積累加情況，執行低精確度模式；此模式之下，系統會關閉不累加的部分積位元硬體，而浮點乘加器的加法運算，則會關閉低權重位元硬體。使用者可以選擇各種需要的精確度模式，產生器可以自動產生其硬體架構與Verilog code，並確保不同精確度間的硬體不會彼此衝突，並且各種運算都能符合所需精確度要求。
當需要產生非最高精確度的硬體架構，產生器會針對不同精確度加入時脈閘控與拴鎖器，當執行這些精確度運算時，加入的控制開關就會將不必要運作的元件關閉，藉此減少非最高精確度模式運算功率消耗。函數插補器執行四種運算其中一種時，只會查詢該運算的表格獲得二次多項式係數。因此可以加上栓鎖器當開關，減少其餘三種運算表格的動態功率消耗。這樣一來，即使進行最高精確度運算時，也可以降低原本的功率消耗。浮點乘加器單獨執行乘法運算時，會加上栓鎖器關閉加法的部分硬體；單獨執行加法運算時，關閉乘法器，減少單獨運算沒使用的硬體功率消耗。
藉由上述多重精確度函數差補器產生器與多重精確度浮點乘加器產生器，可以根據使用者選擇產生所需要的不同精確度硬體架構，並且在能夠容許的誤差範圍內執行較低精確度的運算，以減少功率消耗並延長裝置的使用時間。

A multi-precision function interpolator generator and a multi-precision MAF generator, which is compliant in with the IEEE-754 single precision floating point standard, is proposed in this paper. Users can generate different hardware architecture with multi-precision according to their requirement. Function interpolator provides logarithms, exponentials, reciprocal and square root reciprocal operations. On the other hand, MAF provides multiplication, addition, and multiply-accumulation, and each operation can be calculated in different precisions. The hardware architecture is designed with full pipeline in order to comply with hardware architectures of general digital signal processors (DSPs) and graphic processors (GPUs).
This function interpolator is designed based on the look-up table method. It can get the approximation value of target function through the calculation of quadratic polynomial. MAF combines floating-point multiplication and accumulation into one single unit to execute multiply-accumulation operation. When executing multiplication, it will align the decimal point in addition process at the same time.
Multi-precision function interpolator and MAF not only have the highest precision mode, they also can execute low precision modes. In low precision mode, system will shut down partial product bits hardware components that are not being used. Users can choose different types of the precision levels needed, and generators will automatically create the hardware architectures and Verilog codes. Different hardware for achieving different precision modes would not conflict with each other, and all operations will meet the precision requirement.
When generating the hardware architecture without the highest precision level, the generator will add the clock gating cells and latches for different precision modes. When producing these approximation values, the switches added will shut down the unnecessary components in order to reduce the power consumption. Executing one of the four functions in the function interpolator will only search for its own calculation’s table to find the coefficients of quadratic polynomial. Therefore, the latch can be added as switches to reduce dynamic power consumption of tables for the other three functions. Thus, even when executing in the highest precision level, the power consumption can also be reduced. When MAF only performing multiplications, latches are added to shut down parts of the accumulation hardware. On the contrary, when it only performing accumulations, parts of the multiplication hardware are shutdown to reduce the power consumption.
As mentioned above, the multi-precision function interpolator generator and the multi-precision MAF generator can generate different hardware architectures with different precision modes for different requirement to reduce the power consumption and extend the battery’s lifetime of the device.

論文審定書 i
論文提要 ii
誌謝 iii
摘要 iv
Abstract vi
第一章 概論 1
1.1 研究動機 1
1.2 論文大綱 2
第二章 研究背景 3
2.1 IEEE-754單精度浮點數標準 3
2.2 函數插補器 4
2.2.1 多項式逼近法 4
2.2.2 二次多項式的函數插補器架構 6
2.3 傳統函數插補器 7
2.3.1 多項式係數產生 9
2.3.2 平方器 10
2.3.3 布斯編碼器與部分積分選擇器 12
2.3.4 壓縮樹 14
2.4 浮點乘加器 17
2.4.1 浮點乘法與加法原理 17
2.4.2 傳統浮點乘加器 18
2.4.3 乘法器 20
2.4.4 移位器 22
2.4.5 捨進 23
第三章 函數插補器產生器 24
3.1 基礎的函數插補器 24
3.1.1 基礎的函數插補器部分積排列 24
3.1.2 基礎的函數插補器架構 25
3.2 多重精確度函數插補器產生器實做 26
3.2.1 以「列」為基礎切割 26
3.2.2 以「欄」為基礎切割 33
3.2.3 多重精確度函數插補器產生器實現 35
第四章 浮點乘加器產生器 48
4.1 基礎的浮點乘加器 48
4.2 多重精確度浮點乘加器產生器實做 49
4.2.1 多重精確度乘法器 49
4.2.2 多重精確度加法器 51
4.2.3 多重精確度浮點乘加器產生器實現 52
4.2.4 多重精確度浮點乘加器之運算誤差 53
第五章 實驗結果 55
5.1 實驗步驟與方法 55
5.2 函數插補器驗證與數據比較 56
5.3 浮點乘法器驗證與數據比較 69
第六章 結論與未來研究方向 72
6.1 結論 72
6.2 未來研究方向 72
參考文獻 73

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