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博碩士論文 etd-0716117-154234 詳細資訊
Title page for etd-0716117-154234
論文名稱
Title
具低功耗與高集積密度之垂直通道非傳統互補式金屬氧化物半導體
Vertical Channel Non-Classical CMOS with Low Power Dissipation and High Integration Density
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
155
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2017-07-27
繳交日期
Date of Submission
2017-08-22
關鍵字
Keywords
互補式金屬氧化物半導體、碰穿電晶體、無接面電晶體、高集積密度、低功率消耗、垂直通道
CMOS, punch through transistor, junctionless transistor, high integration density, low power dissipation, vertical channel
統計
Statistics
本論文已被瀏覽 5726 次,被下載 30
The thesis/dissertation has been browsed 5726 times, has been downloaded 30 times.
中文摘要
在本論文中,我們提出一個具有低功率消耗與高集積密度的垂直通道非傳統互補式金屬氧化物半導體。我們將非傳統操作機制中的無接面電晶體(Junctionless transistor, JLMOS)與碰穿電晶體(Punch through transistor, PTMOS)取代傳統互補式金屬氧化物半導體(Complementary metal oxide semiconductor, CMOS)反相器中的負型金屬氧化物半導體電晶體以及正型金屬氧化物半導體電晶體。我們分別探討JLMOS以及PTMOS的操作機制,並整理出兩顆電晶體的開關由臨界電壓(Threshold Voltage)與平帶電壓(Flat Band Voltage)所控制,不同於傳統CMOS的開關機制。
我們設計的垂直通道非傳統互補式金屬氧化物半導體在Q1與Q2的次臨界擺幅(Subthreshold swing)分別達到66 mV/dec與67 mV/dec;開啟電流與關閉電流比(ION/IOFF)達到接近104;功率消耗(Power dissipation) = 2.01 nW。與傳統互補式金屬氧化物半導體與非傳統互補式金屬氧化物半導體(Non-classical complementary metal oxide semiconductor, NCCMOS)比較,不論在單顆電性上的次臨界擺幅、開啟電流與關閉電流比與電路組成上所計算的功率與傳輸延遲時間指標(Power delay product)都還要優秀。我們提出的垂直通道非傳統互補式金屬氧化物半導體擁有垂直架構,能夠比傳統平面式架構有著微縮性的優勢。經由相同設計規則下設計反相器,能夠比傳統互補式金屬氧化物半導體反相器減少56.5 %的製程面積。我們設計的垂直通道非傳統互補式金屬氧化物半導體擁有低功率消耗與高集積密度。
Abstract
In this thesis, we propose a vertical channel non-classical CMOS (VNCCMOS) with low power dissipation and high integration density. Junctionless transistor and punch through transistor replaced conventional NMOS and PMOS respectively in our structure for use in low power supply systems. The operating mechanisms of respective junctionless transistor (JLMOS) and punch through transistor (PTMOS) are further analyzed in depth. The threshold voltage (VTH) and the flat-band voltage (VFB) are used in JLMOS and PTMOS respectively.
This VNCCMOS circuit achieves subthreshold swing = 66 mV/dec and 67 mV/dec of Q1 junctionless transistor and Q2 punch through transistor respectively. Both transistors’s ION/IOFF can be close to 104 at power supply VD = 0.3 V. The VNCCMOS obtain low power dissipation (PD) = 2.01 nW. The power delay product of VNCCMOS is better than conventional planar CMOS (CMOS) and planar non-classical CMOS (NCCMOS). The VNCCMOS with vertical channel is good for scaling down. Our structure can reduced the layout area by 56.5 % compared with conventional CMOS inverter. The VNCCMOS reaches low power dissipation and high integration density.
目次 Table of Contents
中文審定書 i
英文審定書 ii
致謝 iii
摘 要 iv
Abstract v
目 錄 vi
圖目錄 ix
表格目錄 xiv
第一章 導論 1
1.1 研究背景 1
1.2 動機 6
第二章 元件機制與元件操作原理 8
2.1 傳統互補式金屬氧化物半導體反相器架構與操作機制 8
2.1.1 傳統互補式金屬氧化物半導體反相器架構圖 9
2.1.2 傳統互補式金屬氧化物半導體反相器操作機制說明 10
2.2 非傳統互補式金屬氧化物半導體反相器與垂直通道非傳統互補式金屬氧化物半導體反相器架構與操作機制 16
2.2.1 無接面電晶體Junctionless transistor操作機制 16
2.2.2 碰穿電晶體Punch through transistor 操作機制 22
2.2.3 以N型無接面電晶體及N型碰穿電晶體所構成之垂直通道金屬氧化物半導 體反相器操作理論 27
第三章 元件架構設計與製程步驟 31
第四章 電性討論與分析 35
4.1 元件模擬使用之物理模型說明 37
4.2 VNCCMOS-JLQ1之元件電性探討 38
4.2.1 埋入式氧化層厚度tbox對於VNCCMOS-JLQ1之影響 41
4.2.2 共用閘極長度LCG對於VNCCMOS-JLQ1之影響 45
4.2.3 共用閘極高度HCG對於VNCCMOS-JLQ1之影響 46
4.2.4 側壁閘極(Sidewall gate)對於VNCCMOS-JLQ1之影響 48
4.3 VNCCMOS-PTQ2之元件電性探討 50
4.3.1 埋入式氧化層厚度tbox對於VNCCMOS-PTQ2之影響 53
4.3.2共用閘極長度LCG對於VNCCMOS-PTQ2之影響 54
4.3.3共用閘極高度HCG對於VNCCMOS-PTQ2之影響 55
4.3.4 側壁閘極(Sidewall gate)對於VNCCMOS-PTQ2之影響 57
4.4 VNCCMOS數位邏輯閘應用 59
4.4.1 輸入輸出轉移曲線(Voltage Transfer Curve, VTC)與功率消耗(Power Dissipation, PD) 60
4.4.2 七級環形震盪器(7-Ring Oscillator) 64
4.4.3 反相器(Inverter)與延遲時間(Propagation Delay Time, tP) 66
4.4.4 反或閘(NOR Gate) 69
4.4.5 反及閘(NAND Gate) 72
4.4.6 靜態隨機存取記憶體(Static Random Access Memory, SRAM) 75
4.4.7 全加器(Full Adder) 80
4.5 VNCCMOS與平面傳統互補式金屬氧化物半導體、平面非傳統互補式金屬氧化物半導體之比較 82
4.5.1 次臨界擺幅(Subthreshold Swing, SS)與開啟電流/關閉電流(ION/IOFF) 83
4.5.2 雜訊邊界(Noise Margin, NM) 86
4.5.3 功率消耗(Power Dissipation, PD) 90
4.5.4 七級震盪器(7-Ring Oscillator) 91
4.5.5 傳輸延遲時間(Propagation Delay Time, tP) 93
4.5.6 功率與傳輸延遲時間指標(Power Delay Product, PDP) 97
4.5.7 靜態隨機存取記憶體(Static Random Access Memory, SRAM) 98
4.5.8 佈局面積(Layout Area) 103
4.5.9 元件實作與量測結果 105
第五章 結論與未來展望 110
5.1 結論 110
5.2 未來展望 111
參考文獻 112
附錄 121
論文著述 140
參考文獻 References
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