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博碩士論文 etd-0717117-004207 詳細資訊
Title page for etd-0717117-004207
論文名稱
Title
具多晶矽通道之薄膜電晶體與穿隧電晶體的正偏壓溫度不穩定性之比較
Comparison of Positive Bias Temperature Instability between Thin-Film Transistors and Tunnel Transistors with Poly-Si Channel Film
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
53
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2017-07-24
繳交日期
Date of Submission
2017-08-17
關鍵字
Keywords
穿隧式薄膜電晶體、正偏壓溫度不穩定性、多晶矽通道
Poly-Si channel, Tunnel Thin-Film Transistor, Positive Bias Temperature Instability
統計
Statistics
本論文已被瀏覽 5671 次,被下載 35
The thesis/dissertation has been browsed 5671 times, has been downloaded 35 times.
中文摘要
本論文中,藉由傳統薄膜電晶體與穿隧式薄膜電晶體進行正偏壓不穩定性之比較。分別在閘極施以應力0V和15V進行25oC、50oC、75oC三種溫度之量測。由量測結果可知傳統薄膜電晶體隨著溫度增加劣化越嚴重,主要是因為量測過程中,當溫度增加會驅使更多電子往閘極氧化層和多晶矽通道之界面產生碰撞,因而產生更多表面陷阱能態,導致次臨界斜率劣化、臨界電壓產生位移。
然而穿隧式薄膜電晶體在正偏壓不穩定性之量測過程中,閘極施以應力10V在75oC時卻沒有明顯劣化,而當溫度越低時劣化越嚴重,此現象與傳統薄膜電晶體完全相反;主要是穿隧式薄膜電晶體在低溫時載子能量低,需透過陷阱輔助穿隧,因此對陷阱能態多寡影響很大。不過當溫度升高時,載子擁有較高能量可以直接進行能帶間穿隧,而降低陷阱輔助穿隧,所以對陷阱能態數量較不敏感,因此擁有較高的正偏壓不穩定性之免疫力。
Abstract
This study conducts a comparison of positive bias temperature instability between conventional TFT and Tunnel TFT by applying stresses of 10V and 15V on the gate and conducting measurement at the temperatures of 25oC, 50oC, and 75oC. Measurement results show that conventional TFT degradation as temperature rises. This is mainly because during the measuring process, rise in temperature leads to more electron collision at the interface between the gate oxide and poly-Si channel film, increasing interface trap states and in turn causing subthreshold swing degradation and threshold voltage shift.
However, during the positive bias temperature instability measuring process, Tunnel TFT showed no obvious degradation when the gate received 10V of stress at 75oC while degradation as temperature decreased a phenomenon completely opposite to that of conventional TFT. This can mainly be attributed to the fact that tunnel TFT present low carrier energy level at low temperatures, requiring trap-assisted tunneling and thus greatly impacting the number of trap states. Nevertheless, when temperature rises, carriers have higher levels of energy that allows them to directly undergo band-to-band tunneling and reduce trap-assisted tunneling. This leads to their insensitivity towards number of trap states, giving them higher PBTI immunity.
目次 Table of Contents
論文審定書 i
致謝 ii
摘要 iii
Abstract iv
目錄 v
圖目錄 vii
第1章 緒論 1
1.1 前言 1
1.2 多晶矽薄膜電晶體(Poly-Si Thin-Film Transistor) 2
1.2.1 晶粒邊界(Grain Boundary) 2
1.2.2 晶粒改善 3
1.3 短通道效應(Short Channel Effect) 3
1.3.1 汲極引致能障降低(Drain-induced Barrier Lowering,DIBL) 3
1.3.2 擊穿崩潰(Punch Through) 3
1.4 薄膜電晶體之可靠度機制 4
1.4.1 正偏壓應力(Positive Bias Stress,PBS) 4
1.4.2 負偏壓應力(Negative Bias Stress,NBS) 4
1.5 穿隧式場效電晶體(Tunnel Field-Effect Transistor,T-FET) 5
1.5.1 穿隧式場效電晶體載子傳輸機制 5
1.5.2 Shockley-Read-Hall產生與複合 5
1.5.3 陷阱輔助穿隧(Trap-Assisted Tunneling,TAT) 6
1.5.4 能帶至能帶穿隧(Band-To-Band Tunneling,BTBT) 6
1.6 多晶矽穿隧式場效電晶體 7
1.7 動機 7
第2章 實驗步驟與流程 15
2.1 元件製作 15
2.2 電性參數萃取 16
2.2.1 臨界電壓(Threshold Voltage) 16
2.2.2 次臨界擺幅(Subthreshold Swing) 17
2.2.3 開啟電流和關閉電流(On–state Current&Off–state Current) 17
2.2.4 晶粒邊界陷阱能態(Grain Boundary Trap State) 17
2.2.5 界面陷阱能態(Interface Trap State) 18
第3章 結果與討論 24
3.1 常態量測 24
3.2 可靠度量測和參數萃取 24
3.3 傳統與穿隧式薄膜電晶體之正偏壓溫度不穩定性分析(PBTI) 25
3.4 穿隧式薄膜電晶體於正偏壓溫度不穩定性之劣化特性分析 25
3.5 傳統與穿隧式電晶體之溫度效應對於陷阱能態分析 26
第4章 結論 40
參考文獻 41
參考文獻 References
[1] S. Zhang, C. Zhu, J. K. O. Sin, J. N. Li, and P. K. T. Mok, "Ultra-Thin Elevated Channel Poly-Si TFT Technology for Fully-Integrated AMLCD System on Glass," IEEE Transactions on Electron Devices, pp. 569-575, 2000.
[2] M.-C. Liu et al., "SONOS memories with embedded silicon nanocrystals in nitride," Semiconductor Science and Technology, vol. 23, no. 7, p. 075033, 2008.
[3] O. V. Naumova et al., "SOI nanowires as sensors for charge detection," Semiconductor Science and Technology, vol. 25, no. 5, p. 055004, 2010.
[4] I.-W. Wu, T.-Y. Huang, W. B. Jackon, A. G. Lewis, and A. Chiang, "Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation," IEEE Electron Device Letters, vol. 12, pp. 181-183 1991.
[5] W. C.-Y. Ma and Y.-H. Chen, "Performance Improvement of Poly-Si Tunnel FETs by Trap Density Reduction," IEEE Transactions on Electron Devices, vol. 63, no. 2, pp. 864-868, 2016.
[6] G. Fortunato, L. Mariucci, R. Carluccio, A. Pecora, and V. Foglietti, "Excimer laser crystallization techniques for polysilicon TFTs," Applied Surface Science, pp. 95-104, 2000.
[7] Y.-H. Chen et al., "Impact of Crystallization Method on Poly-Si Tunnel FETs," IEEE Electron Device Letters, vol. 36, no. 10, pp. 1060-1062, 2015.
[8] Y.-H. Chen, L.-C. Yen, T.-S. Chang, T.-Y. Chiang, P.-Y. Kuo, and T.-S. Chao, "Low-Temperature Polycrystalline-Silicon Tunneling Thin-Film Transistors With MILC," IEEE Electron Device Letters, vol. 34, no. 8, pp. 1017-1019, 2013.
[9] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices 2nd Edition. Cambridge University Press, 2009.
[10] M.-W. Ma et al., "Reliability Mechanisms of LTPS-TFT With HfO2 Gate Dielectric: PBTI, NBTI, and Hot-Carrier Stress," IEEE Transactions on Electron Devices, vol. 55, no. 5, pp. 1153-1160, 2008.
[11] A. Vandooren, A. M. Walke, A. S. Verhulst, R. Rooyackers, N. Collaert, and A. V. Y. Thean, "Investigation of the Subthreshold Swing in Vertical Tunnel-FETs Using H2 and D2 Anneals," IEEE Transactions on Electron Devices, vol. 61, no. 2, pp. 359-364, 2014.
[12] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices 3rd. WILEY, 2006.
[13] Y.-R. Jhan et al., "Low-Temperature Microwave Annealing for Tunnel Field-Effect Transistor," IEEE Electron Device Letters, vol. 36, no. 2, pp. 105-107, 2015.
[14] A. C. Seabaugh and Q. Zhang, "Low-Voltage Tunnel Transistors for Beyond CMOS Logic," Proceedings of the IEEE, vol. 98, no. 12, pp. 2095-2110, 2010.
[15] K. Chang, "Impacts of Ammonia Plasma Treatment on Tunnel-FET With Poly-Si Channel Film," Department of Electrical Engineering National Sun Yat-sen University Master Theris 2016.
[16] K. Boucart and A. M. Ionescu, "Double-Gate Tunnel FET With High-K Gate Dielectric," IEEE Transactions on Electron Devices, vol. 54, no. 7, pp. 1725-1733, 2007.
[17] L. Chia-Pin, T. Bing-Yue, Y. Ming-Jui, H. Ruei-Hao, and C. Chao-Hsin, "High-performance poly-silicon TFTs using HfO2 gate dielectric," IEEE Electron Device Letters, vol. 27, no. 5, pp. 360-363, 2006.
[18] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, "Conductivity behavior in polycrystalline semiconductor thin film transistors," Journal of Applied Physics, vol. 53, no. 2, pp. 1193-1202, 1982.
[19] R. E. PROANO, R. S. MISAGE, and D. G. AST, "Development and Electrical Properties of Undoped Polycrystalline Silicon Thin Film Transistors," IEEE Transactions on Electron Devices, vol. 36, pp. 1915-1989, 1989.
[20] C. A. Dimitriadis, P. A. Coxon, L. Dozsa, L. Papadimitriou, and N. Economou, "Performance of Thin-Film Transistors on Poly silicon Films Grown by Low-Pressure Chemical Vapor Deposition at Various Pressures," IEEE Transactions on Electron Devices, vol. 39, pp. 598-606, 1992.
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