在現今網路普及的年代，其延伸之應用早已無遠弗屆，而隨著物/車聯網的興起，未來無線網路系統的訊號傳輸，勢必具備高傳輸速率與高精確度，以及更遠的傳輸距離，這使得多重輸入/輸出(Multi-Input Multi-Output, MIMO)技術蓬勃發展；因MIMO接收機系統架構中多數收發天線需相對應數量的主被動電路，造成內部相同功能的分配器元件佔用過多的架構面積。為改善此一缺點，本論文運用微機電系統製程之面型微加工技術設計開發多重功率分配器，將MIMO接收機系統架構中相同功能之分配器元件做整合，使其應用能夠滿足當今無線通訊網路產品輕薄短小之需求。
為使整合之功率分配器於高頻時具有四埠輸出、低損耗與微小化之特性，本論文對元件結構之設計與製程整合提出以下三種方法：(i)主線圈使用兩個中央抽頭式功率分配器，並將其導線互相纏繞以縮減元件面積；(ii)主線圈採懸浮式結構設計，以減少元件與基板間產生之寄生電容所造成的能量損失；(iii)使用具高介電常數材料之氧化鋯薄膜作為端埠匹配電容之介電層以大幅縮減元件面積。本論文所設計開發之功率分配器元件包含底部訊號傳導層、支撐銅柱與介電層，以及頂部訊號傳導層共三層結構堆疊而成，其製程步驟總共包含六次薄膜沉積製程、三次銅電鍍製程、五次黃光微影製程以及四次薄膜蝕刻之結構釋放。
本論文所設計之功率分配器與本實驗室之前期研究成果(宋嘉龍學長，2016)相比，元件面積由原本之2900 μm (L) × 2800 μm (W) × 21 μm (H)大幅縮小至1290 μm (L) × 1060 μm (W) × 24.15 μm (H)，縮減幅度約593%。藉由網路分析儀於10 MHz至8 GHz之頻段量測元件特性，前期所完成之雙層電容式元件，其量測特性於中心頻率2.4 GHz時，四輸出端埠之插入損耗分別為-71.10、-57.25、-50.83與-71.33 dB；而在反射損耗部分，兩輸入端埠分別為-0.34與-0.32 dB，四輸出端埠則分別為-0.82、-0.84、-0.87與-0.69 dB；另外在相位方面，兩輸出端埠之相位差離標準值180°分別相差87.99°與61.42°。後期針對元件結構與製程穩定度予以改善，所完成之單層電容式元件經量測結果顯示，其四輸出端埠之插入損耗分別為-10.89、-12.27、-8.98與-15.98 dB，與雙層電容式相比，分別改善了85、79、82與78%；而在反射損耗部分，兩輸入端埠分別為-1.34與-1.17 dB，改善了294與266%；四輸出端埠則分別為-1.51、-2.09、-7.25與-2.18 dB，亦分別改善了84、149、733與216%；另外在相位方面，兩輸出端埠之相位差則與標準值180°分別僅相差9.93°與0.50°。

Since the Internet of Things (IoT) and Internet of Vehicle (IoV) markets are increasing rapidly, the wireless communication system with higher data rate, information accuracy and farther transmission distance are developed for matching the requirements of the multi-input multi-output (MIMO) techniques. However, there are similar passive and active devices with the same functions consume extra area in the MIMO receiver system. In order to improve the disadvantage, this thesis designed and developed a multiplex power divider replaced two traditional power dividers utilizing the surface micromachining process, and diminish the dimensions of divider for the needs of wireless communications network products.
To realize the power divider with four-phase outputs, low transmission losses and compact size characteristics, the main fabrication processes in this thesis including: (i) Employ two central tapped power divider to reduce the chip size; (ii) Utilize suspended structure to reduce the insertion loss caused by parasitic capacitance between device and substrate; (iii) High dielectric constant material (zirconium oxide) used as the dielectric layer to significantly reduce dimension. This power divider constructed of bottom electrode, supporting posts and top electrode. The main fabrication processes including six thin-film depositions, three copper electroplating, five graphic definitions of photolithography and four etching processes.
Compared with our previous research (Chia-Lung Song, senior, 2016). The chip size is significantly reduced from 2900 μm (L) × 2800 μm (W) × 21 μm (H) to 1290 μm (L) × 1060 μm (W) × 24.15 μm (H), the reduction range is about 593%. The multiplex power divider with 2.4 GHz operating frequency and measured from 10 MHz to 8.0 GHz by network analyzer. There were two generations of the power divider in this thesis. The initial generation with double-layer capacitance showed the four output insertion losses are -71.10, -57.25, -50.83 and -71.33 dB, and -10.89, -12.27, -8.98 and -15.98 dB in the subsequent generation with single-layer capacitance, all the output insertion loss characteristics improved above than 78%. Moreover, the input return losses enhanced from -0.34 and -0.32 dB to -1.34 and -1.17 dB, which improved 294% with early. The output return losses demonstrate -0.82, -0.84, -0.87 and -0.69 dB in the previous generation, and -1.51, -2.09, -7.25 and -2.18 dB in the following generation, which enhanced more than 84%. Compare with the standard phase difference (180°), the initial generation exhibited 87.99° and 61.42°, whereas 9.93° and 0.50° in the subsequent generation.

論文審定書...i
摘要...ii
Abstract...iv
誌謝...vi
目錄...vii
圖目錄...x
表目錄...xvi
第一章 緒論...1
1.1 前言...1
1.2 研究動機與目的...2
1.3 實驗方法與論文架構...4
第二章 功率分配器設計理論分析與材料特性之簡介...5
2.1 功率分配器...5
2.1.1 T型接面功率分配器(T-Junction Power Divider)...5
2.1.2 威爾金森功率分配器(Wilkinson Power Divider)...6
2.1.3 環型功率分配器(Ring Hybrid Power Divider)...9
2.2 變壓器...10
2.3 元件主結構金屬材料之特性...12
2.3.1 導線金屬材料之選擇...12
2.3.2 銅金屬材料之特性...14
2.3.3 銅金屬之沉積技術...15
2.3.4 銅金屬之蝕刻技術...17
2.4 元件電容介電層材料之特性...18
2.4.1 介電材料之選擇...18
2.4.2 氧化鋯材料之特性...20
2.4.3 氧化鋯之沉積技術...22
2.4.4 氧化鋯之蝕刻技術...23
2.5 元件光阻犧牲層材料之特性...24
第三章 懸浮變壓器式微型功率分配器模擬設計與製作...26
3.1 前言...26
3.2 懸浮變壓器式微型功率分配器之特性指標...27
3.3 主結構懸浮螺旋線圈之高頻特性模擬...29
3.4 懸浮變壓器式微型功率分配器之高頻特性模擬...31
3.5 懸浮變壓器式微型功率分配器之光罩佈局設計...35
3.6 懸浮變壓器式微型功率分配器之製程整合...36
3.7 懸浮變壓器式微型功率分配器之製程步驟與參數...37
第四章 實驗結果與討論...56
4.1 懸浮變壓器式微型功率分配器關鍵製程技術之開發...56
4.1.1 銅電鍍沉積技術...56
4.1.2 氧化鋯濺鍍沉積技術...58
4.2 MIM平行板電容雙層結構元件之開發...64
4.2.1 阻擋層之金屬薄膜開孔...71
4.2.2 氧化鋯介電材料之濕式蝕刻...74
4.3 懸浮變壓器式微型功率分配器元件之高頻特性量測...77
4.3.1 製程改善前之量測結果與討論...77
4.3.2 製程改善後之量測結果與討論...85
第五章 結論與未來展望...89
5.1 結論...89
5.2 未來展望...92
參考文獻...93

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