在本篇碩士論文中，我們提出了低功率應用含垂直式雙閘極電流橋之無電容式動態隨機存取記憶體 (Vertical double gate transistor with n-bridge DRAM, VN-DRAM)。此VN-DRAM不像是傳統平面式電流橋架構只有一個閘極可以控制空乏區，我們提出的VN-DRAM擁有雙閘極來控制空乏區，因此在較短的閘極長度可以提升可程式規劃視窗(Programming Window (P.W.))。此外，此垂直架構之雙閘極在製程過程中是可以自我對準的。我們提出的VN-DRAM， 在元件寬度為45奈米跟閘極長度為11奈米的條件下，可程式規劃視窗可以達到  36 µA/µm。此架構擁有兩個P型區使資料延長保存時間 (Retention Time (R.T.))在常溫的時候可以增加到544 奈秒，在高溫358 K的時候可以達到72 奈秒。除此之外，VN-DRAM的最低的偏壓可以被操作在0.95伏特，在此操作偏壓下可以比在操作偏壓為1.2 伏特時減少40 %的功率消耗。我們在此提出操作偏壓微縮優異的新型架構，同時VN-DRAM寫入速度可以達到4 奈秒的快速操作。

In this thesis, we propose a Vertical double gate transistor with n-bridge DRAM (VN-DRAM) for low power applications. Unlike conventional current bridge architecture which has only one sided gate controllability of the depletion region, the proposed VN-DRAM has double gate control of the depletion region which enhances the programming window (P.W.) at shorter gate lengths. Also, the gate can be self-aligned. The proposed VN-DRAM achieves a P.W. of  36 µA/µm for device width of 45 nm at a gate length of 11 nm. VN-DRAM has two p-body regions which can store more holes, the retention time (R.T.) can be improved up to 544 ms at 300 K and 72 ms at 358 K. In addition, the lowest voltage for all operations of the proposed VN-DRAM can be limited to 0.95 V, it can reduce 40 % power consumption for Write ‘1’ operation compared to that of using power supply 1.2 V. Thus highlighting the voltage scalability of the proposed device. VN-DRAM has high speed operation which can reach 4 ns for Write ‘1’ operation.

中文審定書 i
英文審定書 ii
致謝 iii
摘要 iv
Abstract v
Contents vi
List of Figures viii
List of Tables x
Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 4
Chapter 2 Operation Principle 6
2.1 Physical Mechanism Discussion 6
2.2 Memory write mechanism 7
2.2.1 Gate Induced Drain Leakage (GIDL) 7
2.2.2 Impact Ionization (I.I.) 9
Chapter 3 Productions of Device 11
3.1 Process of Device 11
Chapter 4 Research Methods and Results Discussion 13
4.1 Physical Mechanism Model 13
4.2 Architecture Instructions 15
4.3 Operation Mode 19
4.4 I-V Characteristics 23
4.5 Programming Window 25
4.6 Data Retention Time 27
4.7 Write Time 30
4.8 Power Consumption 32
4.9 Disturbance Immunity 36
4.10 Scalability 38
4.11 1T-DRAM Benchmark 40
Chapter 5 Experimental Result and Explore 42
5.1 Design of Mask 42
Chapter 6 Conclusion and Future Work 44
6.1 Conclusion 44
6.2 Future Work 45
References 46
Appendix 55
Explore of Gate-All-Around structure 55
Experiment Measurement and Review 57

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