在本論文中，我們提出一個運用於低偏壓具有抬高本體之碰穿互補式金屬氧化物半導體。利用抬高本體的架構，使得擴散電流受到抑制，以達到低功耗應用。我們利用兩個碰穿電晶體(Punch through transistor, PTMOS)、PTPMOS和PTNMOS分別取代傳統互補式金屬氧化物半導體(Complementary metal oxide semiconductor, CMOS)反相器其中的負型金屬氧化物半導體電晶體(NMOS)與正型金屬氧化物半導體電晶體(PMOS)。其中、我們也深入探討抬高式架構碰穿電晶體的操作機制。我們發現利用抬高本體高度的碰穿電晶體架構將使得擴散電流明顯受到抑制、使得反向器的電性明顯受到改善。
根據模擬結果顯示，我們設計的具有抬高本體之碰穿互補式金屬氧化物半導體，基於鰭長度(Fin length) 20 奈米技術節點，在電源電壓VDD = 0.5 V時，BR-PTPMOS與BR-PTNMOS的開啟電流與關閉電流比(ION/IOFF)分別達到1.61 × 105與5.97 × 105；功率消耗 (Power dissipation) 則為0.18 pW。反觀相同尺寸的傳統CMOS ION/IOFF則分別為1.5 × 105與1.61 × 105；且功率消耗為955 pW。證明我們提出的具有抬高本體之碰穿互補式金屬氧化物半導體能比一般傳統互補式金屬氧化物半導體更省電。至於功率與傳輸延遲時間指標(Power delay product)，我們新技術和傳統CMOS分別為0.126 nW•ns和 27.73 nW•ns ，展示了我們所設計的具有抬高本體之碰穿互補式金屬氧化物半導體能成為未來低功耗應用的候選人之一。

In this thesis, we propose a punch through complementary metal oxide semiconductor (PTCMOS) with a raised body for suppressing diffusion current (BR-PTCMOS) in low power supply applications. Complementary behavior is achieved through two punch-through transistors. The punch-through mechanism of these two transistors is analyzed. The raised body is found to effectively suppress diffusion current.
According to the TCAD simulations, at VDD = 0.5 V, the ION/IOFF ratios are simulated to be 1.61 × 105 for the body-raised punch through PMOS (BR-PTPMOS) and 5.97 × 105 for the body-raised punch through NMOS (BR-PTNMOS) compared with 1.5 × 105 for the NMOS and 1.61 × 105 for the PMOS of conventional CMOS with the same fin length 20 nm. The new device has significant lower power dissipation than a conventional CMOS. A BR-PTCMOS inverter consumes 0.18 pW at VDD = 0.5 V with a power-delay product of 0.126 nW•ns whereas the conventional CMOS consumes 955 pW with a power-delay product of 27.73 nW•ns. Thus, the BR-PTCMOS is an attractive candidate for low power supply applications.

中文審定書 i
英文審定書 ii
致謝 iii
摘　要 iv
Abstract v
Contents vi
Figure Captions ix
Table Captions xiv
Chapter 1　Introduction 1
1.1 Background 1
1.2 Motivation 2
Chapter 2　Operation mechanism 4
2.1 Operation mechanism of BR-PTMOS 4
2.2 Operation mechanism of BR-PTCMOS inverter 10
Chapter 3　Device Design and Fabrication 12
Chapter 4　Simulation Results and Discussion 17
4.1 Electrical discussion of BR-PTPMOS 18
4.1.1 Impact of LFin on BR-PTPMOS 18
4.1.2 Impact of HB on BR-PTPMOS 20
4.1.3 Impact of LSG on BR-PTPMOS 21
4.1.4 Impact of power supply on BR-PTPMOS 22
4.2 Electrical discussion of BR-PTNMOS 24
4.2.1 Impact of LFin on BR-PTNMOS 24
4.2.2 Impact of HB on BR-PTNMOS 26
4.2.3 Impact of LSG on BR-PTNMOS 27
4.2.4 Impact of power supply on BR-PTNMOS 28
4.3 (Ⅰ) Comparison of BR-PTCMOS and the Conventional CMOS 30
4.3.1 Subthreshold Swing (SS) and ON / OFF Current (ION/IOFF) 31
4.3.2 Noise Margin (NM) 33
4.3.3 Power Dissipation (PD) 36
4.3.4 7-Ring Oscillator 37
4.3.5 Propagation Delay Time (tP) and Power Delay Product (PDP) 39
4.3.6 Static Random Access Memory (SRAM) 41
4.4 (Ⅱ) Comparison of BR-PTCMOS and the Conventional CMOS 43
4.4.1 Subthreshold Swing (SS) and ON / OFF Current (ION/IOFF) 43
4.4.2 Noise Margin (NM) 46
4.4.3 Power Dissipation (PD) 49
4.4.4 7-Ring Oscillator 50
4.4.5 Propagation Delay Time (tP) and Power Delay Product (PDP) 52
4.4.6 Static Random Access Memory (SRAM) 54
4.5 NOR Gate 56
4.6 NAND Gate 58
4.7 Full Adder 60
4.8 Comparison of PTCMOS and the BR-PTCMOS 62
4.8.1 Subthreshold Swing (SS) and ON / OFF Current (ION/IOFF) 62
4.8.2 Noise Margin (NM) 64
4.8.3 Power Dissipation (PD) 67
4.8.4 7-Ring Oscillator 67
4.8.5 Propagation Delay Time (tP) and Power Delay Product (PDP) 69
4.8.6 Static Random Access Memory (SRAM) 70
Chapter 5　Conclusion and Future Work 72
5.1 Conclusion 72
5.2 Future Work 73
Reference 74
Appendix 84

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