摘 要
本篇論文提出一個可操作在解析度十位元且取樣頻率為1MHz之逐次趨近型式類比數位轉換器(10bit 1MSample/sec Successive Approximation A/D converter)。首先，我們使用一個具有高輸入阻抗的比較器做為新的寬擺幅R-2R數位類比轉換器的負載。由於寬擺幅R-2R數位類比轉換器的負載極大使得原本使用在數位類比轉換器的運算放大器可被省略掉，因此可用擺幅及數位類比轉換器的速度皆得到提昇，且新的寬擺幅R-2R數位類比轉換器包含新的開關電路和匹配電阻可以使新的寬擺幅R-2R數位類比轉換器具有更精確的分壓，使得數位類比轉換器的準確度提昇。為了得到高準確度的取樣值以提供給比較器，我們提出一個對時脈不敏感的兩倍取樣保持電路。我們使用具有高增益、寬擺幅的運算放大器及含有dummy的類比開關和對時序不敏感的技術來降低誤差及提昇準確度。最後，我們將改良的電路用於類比數位轉換器中使得可用擺幅範圍、速度、準確度等都已被提昇。

本論文所設計之類比數位轉換器採用台灣積體電路製造公司(TSMC) 0.35μm 1P4M CMOS製程來實現，且供應電壓為3.3V。於取樣速度1MHz下，類比至數位轉換的操作電壓範圍為0.8至2.9V，微分非線性誤差約 0.5LSB，積分非線性誤差約 1LSB，而消耗功率為8mW。

Abstract
A 10-bit 1MSample/sec successive approximation A/D converter is described in this thesis. First, by a comparator designed with high input impedance is used for the load of the modified wide-swing R-2R D/A converter. The modified wide-swing R-2R D/A converter possesses a high impedance load thus the op-amp is used in the D/A converter can be neglected. Therefore, the usable swing range and the convertible speed are improved and the power consumption is reduced. Secondary, the modified wide-swing R-2R D/A converter that contains modified switch-circuit and matched-component is used to obtain the good voltage division thereby improving the accuracy. Finally, the modified timing skew-insensitive double-sampling S/H circuit is used to sample a high precision signal to the comparator. This modified timing skew-insensitive double-sampling S/H circuit consists of high-gain high-swing op-amp, CMOS dummy switches, and timing skew-insensitive technique for upgrading the precision and swing range. By using these improved circuits the overall speed, accuracy and swing range are improved.

The proposed successive approximation A/D converter is designed by TSMC 1P4M 0.35μm CMOS process, and it operates at 3.3V power supply voltage with 0.8 to 2.9V reference voltage. The simulation results show that DNL is 0.5LSB, INL is 1LSB, and the power consumption is 8mW.

Contents
Chapter 1 Introduction……………………………1
Chapter 2 Sub-Circuits for Successive Approximation A/D Converter…………6
2.1 Analog MOS Switch………………………6
2.2 Non-overlap Clock Generator and pulse generator………8
2.3 Double-Sampling S/H circuit…………………………………10
2.4 Comparator Circuit…………………………12
2.5 Successive Approximation Register…14
2.6 Wide-Swing Current-Mode R-2R D/A Converter……21
Chapter 3 Modified Double-Sampling S/H Circuit and Modified Wide-Swing R-2R D/A converter………24
3.1 Analog CMOS Dummy Switch……………………24
3.2 The Operational Amplifier Design…………26
3.3 Modified Double-Sampling S/H circuit………30
3.4 Modified Wide-Swing R-2R D/A Converter…33
Chapter 4 Simulation Results………………………39
Chapter 5 Conclusion…………………………………44
Reference………………………………………………45
Appendix A……………………48
Appendix B…………………………………56

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