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博碩士論文 etd-0718114-165103 詳細資訊
Title page for etd-0718114-165103
論文名稱
Title
高效能高基數之字組式蒙哥馬利模數乘法器
High-performance High-radix Word-based Montgomery Modular Multipliers
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
82
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2014-07-22
繳交日期
Date of Submission
2014-08-18
關鍵字
Keywords
公開金鑰密碼系統、RSA密碼系統、高基數字組式蒙哥馬利乘法器、蒙哥馬利模數乘法器
Public-key Cryptosystems, RSA Cryptosystems, High-radix Word-based Montgomery Modular Multiplier, Montgomery Modular Multiplier
統計
Statistics
本論文已被瀏覽 5641 次,被下載 547
The thesis/dissertation has been browsed 5641 times, has been downloaded 547 times.
中文摘要
現今隨著網際網路的蓬勃發展,人類的生活已經跟網路脫離不了關係,而人類的許多活動也轉而透過網路進行。隨著電子商務和電子簽證的網路交易行為愈來愈頻繁,資訊安全也在網際網路越來越受重視。RSA公開金鑰密碼系統是一個傳統的加解密系統,它使用簡單的模數指數運算,以確保資料傳遞的隱密性及安全性。
但此演算法為了足夠的安全性,通常要求位元為1024或2048位元以上,以軟體執行如此龐大位元的運算,是非常消耗成本以及時間的。本論文以提升速度為訴求,將此演算法設計成硬體,以減少大位元模數乘法運算時間和硬體耗能。RSA公開金鑰密碼系統主要是由模數指數運算所組成,而模數指數運算的最主要核心運算則是模數乘法運算。蒙哥馬利演算法則是透過簡單的加法和右移去實現乘法模數運算,大大降低了硬體設計的困難度 。
本論文結合了高基數蒙哥馬利乘法器以及多重字組式蒙哥馬利乘法器的硬體架構,除了透過高基數讓原本需要花費大量時脈週期的乘法模數硬體得以使用更少的時脈週期去完成一次乘法模數運算,又結合了多重字組式的架構,改善原本1024位元或2048位元所形成的大量扇出(fanout)的問題。除此之外,多重字組蒙哥馬利乘法器架構的延遲時間(delay),也因為把一次1024位元的運算分割成以16位元、32位元或64位元為一組的多重字組的架構而有所減少,使得硬體得以更快的速度完成模數乘法運算。
關鍵詞:RSA公開金鑰密碼系統、蒙哥馬利乘法器、多重字組式蒙哥馬利乘法器、高基數蒙哥馬利乘法器
Abstract
Nowadays, with the evolution of the internet,network becomes an important role in human's life. Because more and more E-commerce and electronic transaction are implemented in the internet, the security in the internet is also more and more important.
RSA public-key cryptosystems,is a traditional cryptosystem.It use very simple modulus to ensure the data transfer security and safety.For security reason, RSA operand sizes need to be 1024 bits or greater.But a lot of resources and times are required if we implement it in the software.For higher speed and lower power cosumption , we implement this algorithm in the hardware to improve the performance.
RSA public-key cryptosystem consists of modular exponentiation,which is usually achived by repeated modular multiplications. Modular multiplication algorithm is composed of simple addition and shift operations to lower the difficulty of hardware design.
This thesis combines the high-radix Montgomery architecture and word-based architectue. Through high-radix design,it makes the number of clock cycles smaller.Moreover,it solves the “large fan-out” problem through word-based design.We also lower the hardware delay by cutting 1024-bit operand to 16-bit, 32-bit or 64-bit words to be a word-based architecture. By this architecture , we can ahchive a high performance to accomplish a modular multiplicand iteration.

Keywords : RSA Public-Key Cryptosystems, Montgomery's Algorithm,Word-Based Montgomery Modular Multiplier, High-Radix Montgomery Modular Multiplier
目次 Table of Contents
目錄
第一章 緒論 1
1.1 研究動機 1
1.2 論文大綱 3
第二章 研究背景 4
2.1 RSA公開金鑰密碼系統 4
2.2 蒙哥馬利演算法 6
2.3 進位節省蒙哥馬利演算法 8
2.3.1 5-to-2 CSA蒙哥馬利演算法及架構 9
2.3.2 4-to-2 CSA蒙哥馬利演算法及架構 10
2.4 字組式蒙哥馬利演算法及架構 12
2.4.1 字組式蒙哥馬利演算法 14
2.4.2 字組式蒙哥馬利乘法器架構 16
2.4.3 字組式蒙哥馬利演算法的資料相依性 16
2.5 基數4蒙哥馬利構 19

第三章 高效能高基數之字組式蒙哥馬利乘法器 23
3.1 高基數蒙哥馬利演算法及硬體架構 23
3.2 High radix booth 編碼 26
3.3 Radix-2的方式去模擬高基數蒙哥馬利乘法器 28
3.4 高基數蒙哥馬利的編碼構造 32
3.5 高基數蒙哥馬利乘法器硬體架構 34
3.6 低延遲技術 35
3.6.1 預先計算之低延遲技術 35
3.6.2 重新排程之低延遲技術 37
3.6.3 Tsai採用的低延遲技術 .40
3.7 平衡樹架構(balance tree structure) 42
3.8 指數演算法 44
第四章 提出的演算法及硬體架構設計 47
4.1 提出的高基數之字組式蒙哥馬利乘法演算法 47
4.2 演算法之效能分析 51
4.3 提出的高基數之字組式蒙哥馬利乘法器架構 52
4.3.1 提出的字組式蒙哥馬利乘法器整體架構 52
4.3.2 各種處理單元硬體設計 54
4.3.3 高基數字組式蒙哥馬利乘法器PE架構 56
4.4 balance tree 架構 57

第五章 實驗數據 59
5.1 實驗步驟與方法 59
5.2 實驗結果 61
5.2.1 Delay與Area隨著基數增長的分析 66
第六章 結論與未來研究方向 68
6.1 結論 68
6.2 未來研究方向 68
參考文獻 69
參考文獻 References
參考文獻
[1] R. L. Rivest, A. Shamir, and L. Adleman, “A method for obtaining digital signature and public-key cryptosystems,' Communications of the ACM, vol. 21, pp. 120-126, Feb. 1978.
[2] P. L. Montgomery, “Modular multiplication without trial division,” Mathmatics Computation, vol. 44, pp. 519-521, Apr. 1985
[3] C. D. Walter, “Montgomery exponentiation needs no final subtractions,” Elextron. Lett., vol. 32, no. 21, pp. 1831-1832, Oct. 1999.
[4] T. W. Kwon, C. S. You, W. S. Heo, Y. K. Kang, and J. R. Choi, “Two implementation methods of a 1024-bit RSA cryptoprocessor based on modified Montgomery algorithm,” in Proc. IEEE Int. Symp. Circuits Syst., May 2001, vol. 4, pp. 650-653.
[5] A. Cilardo, A. Mazzeo, L. Romano, and G. P. Saggese, “Carry-save Montgomery modular exponentiation on reconfigurable hardware,” in Proc. Des., Autom. Test Eur. Conf. Exhibition, Feb. 2004, vol. 3, pp.206-211.
[6] C. McIvor, M. McLoone, and J. V. McCanny, “Modified Montgomery modular multiplication and RSA exponentiation techniques,” IEE Proc. Computers and Digital Techniques, vol. 151, no. 6, pp. 402-408, Nov. 2004.
[7] P. Kornerup, “High-Radix Modular Multiplication for Cryptosystems,” Proc. IEEE Symp. Computer Arithmetic, pp. 277-283, Jun 1993.
[8] R. V. Kamala and M. B. Srinivas, “High-Throughput Montgomery Modular Multiplication,” IFIP International Conference on Very Large Scale Integration, pp. 58-62, Oct. 2006.
[9] A. F. Tenca and C. K. Koc, “A scalable architecture for modular multiplication based on Montgomery’s algorithm,” IEEE Tans. Computers, vol. 52, no. 9, pp. 1215-1221, Sept. 2003.
[10] A. F. Tenca, and A. Tawalbeh, “An efficient and Scalable Radix-4 Modular Modular Multiplier Design Using Recoding Techniques,” Proc. Asilomar Conf. Signals, Systems, and Computers, pp. 1445-1450, Nov. 2003.
[11] D. Harris, R. Krishnamurthy, S. Mathew, and S. Hsu, “An improved unified scalable radix-2 Montgomery multiplier,” IEEE Symp. Computer Arithmetic, pp. 1196-1200, Jan. 2005.
[12] N. Pinckney and D. Harris, “Parallelized radix-4 scalable Montgomery multipliers,” J. Integrated Circuits and Syst., vol. 3, no. 1, pp. 39-45, Mar. 2008.
[13] P. Amberg, N. Pinckney, and D. M. Harris, “Parallel High-Radix Montgomery Multipliers,” Proc. Asilomar Conf. Signals, Systems, and Computers, pp. 772-776, Oct. 2008.
[14] M. Huang, K. Gaj, and T. El-Ghazawi, “New Hardware Architectures for Montgomery Modular Multiplication Algorithm,” IEEE Trans. Computer, vol. 60, no. 7, pp. 923-936, July 2011.
[15] M. D. Shieh and W. C. Lin. “Word-Based Montgomery Modular Multiplication Algorithm for Low-Latency Scalable Architecutures,” IEEE Trans. Computers, vol. 59, no. 8, pp. 1145-1151, Aug. 2010.
[16] S. H. Wang, W. C. Lin, J. H. Ye, and M. D. Shieh, “Fast Scalable Radix-4 Montgomery Modular Multiplier,” IEEE International Symposium Circuits and Systems, May 2012, pp. 3049-3052.
[17] 張凱程, “適用於RSA加解密系統之高效能低功率可調式模數乘法器,” 國立中山大學, 碩士論文, July 2010.
[18] 陳佳妏, “低耗能多重字組模數乘法器之設計,” 國立中山大學, 碩士論文, July 2012.
[19] T. Blun and C. Paar, “Montgomery Modular Exponentiation on Reconfigurable Hardware,” Proc. 14th IEEE Symp. Computer Arithmetic, Apr. 1999, pp. 70-77.
[20] C. Walter, “Systolic Modular Multiplication,” IEEE Trans. Computers, vol. 35, no. 1, pp. 1-12 Jan, 1986.
[21] CIC Referenced Flow for Cell-based IC Design, National Chip Implementation Center, Hsinchu, Taiwan, 2008.
[22] TSMC 0.90-μm (CL090G) Process 1.2-Volt SAGE-XTM Standard Cell Library Databook, Artisan Components, Sunnyvale, CA, Jan. 2004.
[23] 邱昶騰, “高效能高基數蒙哥馬利模數乘法器,” 國立中山大學, 碩士論文, July 2013.
[24] 蔡嘉和, “高效能基數四之字組式蒙哥馬利模數乘法器,” 國立中山大學, 碩士論文, July 2014.
[25] 許桓偉, “適用於RSA 加解密系統之高效能低功率模數乘法器,” 國立中山大學, 碩士論文, 2011.
[26] 許弘譯, “適用於RSA 密碼系統的高效能基數-4 蒙哥馬利模數乘法器,” 國立 中山大學, 碩士論文, 2011.
[27] G. Sassaw, C.J. Jimenez, and M. Valencia, “High Radix Implementation of
Montgomery Multipliers with CSA,” International Conference on Microelectronics (ICM), 2010.
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