在本論文提出了一種具有低操作偏壓，應用於非傳統凹入閘極共享摻雜互補式金氧半反向器稱為凹入閘極共享摻雜互補式金氧半(RUCMOS)。我們設計一個凹入閘極NMOS (RNMOS)與凹入閘極碰穿NMOS (RPTNMOS)形成RUCMOS，這兩顆電晶體在源極與汲極有相同的摻雜，凹槽架構可以克服短通道效應，凹入閘極碰穿N型電晶體取代傳統的P型電晶體，使用碰穿機制具有開關能力並可以明顯地改善擺幅與電性。
根據模擬軟體在10 nm時，RNMOS和RPTNMOS分別在0.3 V，達到63 mV/dec 和65 mV/dec，開啟電流與關閉電流比(ION/IOFF)達到104，在傳輸延遲時間上，RUCMOS比CMOS快47.2 %，同時功率消耗比CMOS低59.6 %。除此之外，於CMOS相比RUCMOS的局部面積減少48 %，RUCMOS的7級振盪器可以達到287MHz，CMOS只有35.7MHz。

This thesis presents a non-classical recessed-gate CMOS inverter with unique shared contact and low power supply applications, which called recessed-gate unique-shared CMOS (RUCMOS). We design a recessed-gate NMOS (RNMOS) and a Recessed-gate Punch-Through NMOS (RPTNMOS) to form the RUCMOS. These two transistors have the same low doping source, and drain. RNMOS having recessed structure can greatly overcome short channel effects. RPTNMOS replaces the conventional PMOS, which uses punch through mechanism for on/off behavior. It also has recessed structure which can improve its subthreshold swing and performance significantly. According to the TCAD simulation, the subthreshold swing of 10 nm RNMOS and 10 nm RPTNMOS are 63 mV/dec and 65 mV/dec respectively at power supply VD = 0.3 V. The ION/IOFF of the RUCMOS can be close to 104, which is almost the same as that of RUNOS. Also, RUCMOS inverter exhibits the propagation delay time (TP) 47.2 % faster than that of the conventional CMOS inverter. Meanwhile, the power dissipation is 59.6 % lower than that of the conventional CMOS inverter. Besides, the layout area of the novel inverter is significantly reduced about 48% when compared with the conventional CMOS inverter. For 7-stages RUCMOS ring counter, the oscillator frequency can achieve up to 287 MHz rather than 35.7 MHz for its CMOS counterpart.

中文審定書 i
英文審定書 ii
致 謝 iii
摘　 要 iv
Abstract v
目　錄 vi
圖目錄 ix
表目錄 xvi
第一章、導論 1
1.1 研究背景 1
1.2 動機 5
第二章、物理機制與元件操作原理 6
2.1 元件物理機制 6
2.2 傳統互補式金氧半反向器元件 7
2.2.1 傳統互補金氧半反向器操作機制 8
2.3 碰穿機制的理論 14
2.4 凹入閘極架構應用與機制 15
2.4.1 凹入閘極碰穿機制 16
2.4.2 凹入閘極反轉機制 19
2.4.3 非傳統凹入閘極共享摻雜互補式金氧半反向器 22
第三章、元件架構設計與製程方法 24
第四章、電性討論與分析結果 27
4.1 元件模擬與物理模型說明 28
4.2 RUCMOS電性討論 29
4.2.1 RPTNMOS電性討論 29
4.2.2 RNMOS電性討論 31
4.3 RUCMOS幾何分析 33
4.3.1 RPTNMOS超薄本體於凹入閘極深度與偏壓探討 33
4.3.2 RPTNMOS薄本體於凹入閘極深度與偏壓探討 36
4.3.3 RPTNMOS厚本體於凹入閘極深度與偏壓探討 39
4.3.4 RPTNMOS於不同厚度本體與凹入閘極深度比較 42
4.4 RNMOS模擬幾何分析與電性討論 43
4.4.1 RNMOS超薄本體於凹入閘極深度與偏壓探討 43
4.4.2 RNMOS薄本體於凹入閘極深度與偏壓探討 46
4.4.3 RNMOS於凹入閘極深度與偏壓探討 49
4.4.4 RNMOS於不同厚度本體與凹入閘極深度比較 52
4.5 RUCMOS數位邏輯閘電路 53
4.5.1 雜訊邊界 55
4.5.2 輸入輸出轉移曲線(Voltage Transfer Curve, VTC)與功率消耗(Power Dissipation ,PD)與本質增益(Intrinsic gain) 56
4.5.3 反相器(Inverter)與延遲時間(Propagation Delay Time, TP) 59
4.5.4 七級環形震盪器(7-Ring Oscillator)與操作頻率 62
4.5.5 反或閘(NOR Gate) 64
4.5.6 反及閘(NAND Gate) 66
4.5.7 全加器(Full adder) 68
4.5.8 靜態隨機存取記憶體(Static Random Access Memory, SRAM) 70
4.6 RUCMOS與CMOS之元件探討 75
4.6.1 輸入特性曲線圖分析與電壓轉換特性曲線(VTC)之比較 78
4.6.2 短通道效應30nm微縮至10nm之比較 84
4.6.3 具先進元件之次臨界擺幅(Subthreshold Swing, S.S.)與汲極引致的位能障下降(Drain-Induced-Barrier-Lowering, DIBL)與操作偏壓比較 92
4.6.4 動態功率消耗(Power Dissipation, PD)、雜訊邊界(Noise margin)、本質增益(Intrinsic gain)之比較 93
4.6.5 反相器(Inverter)與延遲時間(Propagation Delay Time, TP )之比較 96
4.6.6 七級環形震盪器(7-Ring Oscillator) 99
4.6.7 功率與傳輸延遲時間(Power Delay Product,PDP) 100
4.6.8 反或閘(NOR Gate)之比較 101
4.6.9 反及閘(NAND Gate)之比較 102
4.6.10 全加器(Full adder)之比較 103
4.6.11 靜態隨機存取記憶體(Static Random Access Memory, SRAM)之比較 104
4.7 反向器之佈局面積之比較 108
4.8 元件實作結果與量測 109
第五章、結論與未來展望 113
5.1 結論 113
5.2 未來展望 115
參考文獻. 116
附錄 126
論文著述. 128

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