在本論文中，藉由 Sentaurus TCAD 12.0軟體工具來設計元件架構與驗證記憶體表現。我們提出了具垂直電流橋和本體在閘極上之無電容式隨機存取記憶體。(Vertical Transistor with N-Bridge and Body on Gate DRAM, BOG-DRAM)。元件使用垂直式通道的架構可以減少短通道效應，且具備足夠製程微縮性。在閘極上的儲存區可以充分利用空間，因為閘極與儲存區在同一個垂直方向。而不需要在旁側製作儲存區，避免了未來元件微縮性不足的缺點。
傳統平面式電流橋元件在儲存區隨著元件微縮後，兩側的汲極和源極變寬使得串聯電阻變小且難以關閉讀取電流，上述原因使得傳統平面電流橋元件可程式規劃視窗降低。因此在微縮化後傳統電流橋元件可程式規劃視窗大幅退化。而我們所提出的BOG-DRAM元件為垂直式架構元件特性受微縮化影響較小，此外沿著儲存區與隔離氧化層沉積一層厚度均勻的通道，三側通道層可以提升寫入速度並增加可程式規劃視窗。
通道層使用N-type channel doping，可以使製程方面較簡單減少隨機摻雜分布變異性(Random Dopant Fluctuation variability) 。而使用自我對準的隔離氧化層，可以減少(Shockley-Read-Hall recombination)，使得元件的資料延長保存時間(Data Retention Time)有較好的表現。在功率消耗的改善方面，BOG-DRAM元件除了在抹除時僅需施加閘極偏壓可以降低在抹除時的功率消耗。我們探討了各個記憶體操作狀態下的功率消耗。更進一步我們研究了在不同功函數下功率消耗的表現，透過功函數偏移降低操作電流達成低功率消耗的應用。

In this thesis, we use Sentaurus TCAD 12.0 software tool to design memory device. We proposed the Vertical Transistor with N-Bridge and Body on Gate DRAM. The device with vertical channel can reduce short channel effect and improve scalability. The storage region on gate can utilize space efficiently. The gate and storage region located at the same direction. So, the device won’t need to fabricate storage at three-wide channel. This design can avoid the poor scalability. Besides, the storage region which near the gate.
When conventional current bridge device’s storage region reduces, source and drain becomes wider. Therefore, device’s series resistance decreases and hard to deplete channel. BOG-DRAM with vertical structure has high scalability compare to planar device. Besides, we deposit uniform channel layer along isolation oxide layer and storage region. Three-wide channel can improve device’s writing time and programming window.
We use n-type doping to make channel layer can achieve easy process and reduce random doping fluctuation variability. The self-aligned isolation oxide layer can improve data retention time. In order to improve power consumption, BOG-DRAM has low power consumption. Because it just need to bias gate voltage to exclude holes. We also investigate memory’s power consumption in the different operation state. Furthermore, we research power consumption’s variation as work function offset. We use work function offset to achieve low power application.

中文論文審定書 i
英文論文審定書 ii
致謝 iii
摘要 iv
Abstract v
目錄 vi
圖次 viii
表次 x
第一章 導論 1
研究背景 1
無電容式1T-DRAM文獻回顧 4
動機 11
論文架構 13
操作原理 14
浮體效應 14
記憶體寫入機制 15
撞擊游離(Impact Ionization)機制 15
寄生BJT(Parasitic BJT)機制 16
閘極引致汲極漏電流(GIDL)機制 18
整合式撞擊游離和閘極引致汲極漏電流機制 19
穿隧場效應電晶體操作機制 21
第三章 元件製作 23
模擬元件說明 23
元件實際製程 23
第四章 研究方法與結果討論 26
物理機制模型 26
BOG-DRAM元件架構說明 29
BOG-DRAM元件之操作方式 31
元件基本特性 36
輸入特性曲線 36
輸出特性曲線 37
可程式規劃視窗 (Programming Window) 39
資料延長保存時間 (Data Retention Time) 43
溫度影響 (Temperature Influence) 48
寫入速度 (Write Time) 51
元件功率消耗 (Power consumption) 54
干擾抵抗性 (Disturbance Immunity) 63
微縮化探討 (Scalabilty) 67
近年來各個1T-DRAM論文的邊際探討(Benchmark) 74
第五章 實作結果與探討 76
元件光罩規劃 76
元件特性量測 78
第六章 結論與未來展望 80
結論 80
未來展望 81
參考文獻 82
附錄 91
論文著述 94

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