本篇論文提出一個可以操作在3.3伏特供應電壓，解析度8位元且取樣頻率為250MHz 之同步比較型電流模式類比數位轉換器(3.3V 8-bit 250MSample/sec Synchronous Comparison Current Mode Analog to Digital Converter)。此ADC設計架構是以4位元同步比較型類比數位轉換器為基礎，此4位元同步比較型ADC架構包括了RGC電流鏡、Thermometer DAC、參考電流源、電流比較器。此4位元同步比較型ADC主要是設計4組Thermometer DAC電路用以同時產生出4組4位元的參考電流Iref，並同時與輸入電流Iin比較，產生出4位元數位輸出碼。此同步比較型類比數位轉換器的優點是以非迴授方式預先由輸入電流Iin量化出之Thermometer碼控制Thermometer DAC產生出所需之參考電流Iref，用以完成高速轉換與同步輸出，同時Thermometer DAC改進Successive Approximation ADC與Variable Threshold Flash ADC中，以輸出二進碼迴授制控加權式DAC所造成之突波與保證一定單調性。在此論文中，8位元ADC是由2組4位元同步比較型ADC所組成，級與級之間是以Sub-ranging的架構所連結，由於不需要取樣和保持電路，所以此結構可達到高速的轉換速度。經由HSPICE的模擬結果得知此IADC 可達到8位元的解析度和250MHz的取樣頻率。

本論文裡所設計的同步比較型類比數位轉換器是使用台灣積體電路製造公司(TSMC) 0.35μm 2P4M 的CMOS 製程。其佈局面積為 420um × 550um ，供應電源為3.3V，功率消耗為13.24mW，微分非線性誤差約為+/- 0.5LSB，積分非線性誤差約為+/- 0.65LSB。

A 3.3V 8-bit 250MSample/sec synchronous comparison current-mode analog to digital converter is described in this thesis. The high bits and low bits are realized by two 4-bit synchronous comparison A/Ds. The 4-bit ADC has 4 reference output, which are compared with Iin, to carry out 4-bit synchronous digital output. The reference produce circuit architecture comprises a quantification current source circuit and a thermal-to-analog (DAC) circuit. In this IADC architecture, each 4-bit pipelined stage consists of current-mirror circuits, quantification current source, and current comparator elements. This architecture can achieve a very high conversion rate due to the lack of sample/hold circuit. From HSPICE simulation results, the proposed IADC can achieve 8-bit resolution with 250MHz sampling rate. It is designed by using TSMC 0.35μm COMS 2P4M technology. It occupies an area of 420um × 550um and has power consumption of 13.24mW from a 3.3-V supply. That DNL is +/- 0.5LSB, and INL is +/- 0.65LSB are achieved.

Source : VLSI 2005 submitted.

第一章 導論...... . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..1
1.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.2 以往相關之研究、結果. . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1.3 目前企圖改進的方式. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.4 研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
第二章 常見類比數位轉換器之各種架構. . . . . . . . . . . . . . 5
2.1 類比數位轉換器的分類. . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.2 逐步逼近類比數位轉換器架構比較. . . . . . . . . . . . . . . . . . .6
2.2.1 Flash ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.2.2 Pipeline ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.3 本論文提出之ADC特性. . . . . . . . . . . . . . . . . . . . . . . . . . . .7
第三章 基本觀念. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .8
3.1 Successive Approximation ADC架構與演算法. . . . . . . . . . . .8
3.2 可變臨界式類比數位轉換器架構與演算法. . . . . . . . . . . . . .11
3.2.1 架構說明. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2.2 演算法. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.3 結語. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
第四章 電流模式同步比較型ADC之電路設計. . . . . . . . . . . . . . .14
4.1 電流模式之同步比較型類比數位轉換器. . . . . . . . . . . . . . .14
4.2 電流鏡. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.2.1 簡單型電流鏡(SCM) . . . . . . . . . . . . . . . . . . . . . . . . .23
4.2.2 串疊式電流鏡(CCM) . . . . . . . . . . . . . . . . . . . . . . . . .24
4.2.3 調節串疊式電流鏡(RGCM) . . . . . . . . . . . . . . . . . . . .25
4.3 數位類比轉換器(DAC) . . . . . . . . . . . . . . . . . . . . . . . . .31
4.3.1 Binary-weighted Current-Scaling DAC . . . . . . . . . .31
4.3.2 Thermometer-Code Current-Steering DAC . . . . . . . . . .32
4.4 電流比較器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.5 四位元同步比較型ADC整體輸出模擬結果. . . . . . . . . . . . . . .41
4.6 八位元同步比較型ADC之結構. . . . . . . . . . . . . . . . . . . .43
第五章 整體八位元ADC實驗模擬結果. . . . . . . . . . . . . . . . . . . .45
5.1 佈局. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
第六章 結論與未來研究方向. . . . . . . . . . . . . . . . . . . . . . . . . .50
參考文獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

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