在此論文中，我們製作具有多重奈米線通道(multiple nanowire channels)與輕摻雜汲極(Lightly-Doped Drain)結構的短通道(閘極長度為0.5um)複晶矽薄膜電晶體(poly-Si TFTs)，並研究在具有不同通道寬度和數目下，元件的操作特性。由實驗結果發現，在同為閘極長度(gate length)為0.5 um 下，具有十條奈米導線通道（每條寬度為67 奈米）的複晶矽薄膜電晶體 (M10 TFT)，展現出較其他不同通道寬度和數目的複晶矽薄膜電晶體，較優越且較穩定的電特性。包括有較高的開關電流比(>109)，較陡峭的次臨界導通斜率(Subthreshold Swing)，極小的汲極導致能障下降 (Drain-Induced Barrier Lowing)，較佳的糾結效應(kink-effect)抑制能力。
進一步地，我們探討利用多重閘極(multi-gate)配合多條奈米線(nanowire)通道之圖案相依金屬誘化側向結晶薄膜電晶體的結構。在實驗結果中顯示，多重閘極搭配十條奈米線通道可進一步的提升元件特性，如具有有更低的漏電流、更高的開關電流比、更低的臨界電壓、更為陡峭的次臨界斜率，並可同時抑制紐結效應(Kink effect)，以及具有較佳的可靠度。總結之，將元件圖案相依金屬誘化側向結晶薄膜電晶體製程中多加一道氨電漿處理，以及改變單一閘極為多重閘極結構，皆可大幅提升元件特性以及降低薄膜電晶體之不理想效應。此元件圖案相依金屬誘化側向結晶薄膜電晶體的製程技術，可與現今的互補式金屬氧化物半導體(CMOS)製程技術相結合，而且不必再添加額外的光罩。此高效能之元件圖案相
依金屬誘化側向結晶薄膜電晶體將可應用在主動式矩陣液晶顯示器以及三維立體之金氧半場效電晶體（3D MOSFET）積體電路元件上。除此之外，我們也研究複晶矽薄膜電晶體在不同溫度與施加電壓下，其漏電流的物理機制。另外我們為了能夠解釋完整，還去模擬不同結構的電場模擬圖。實驗結果顯示有奈米線通道結構的薄膜電晶體，其漏電流要比非奈米線通道的要來的大；而具有多重閘極結構電晶體的漏電流要比單一閘極結構的要來得小。我們從模擬電場圖可以得知，會造成這些現象都是因為在汲極端的電場改變導致。

In this thesis, we study the electrical characteristics of a series of polysilicon thin-film transistors (poly-Si TFTs) with different numbers of multiple channels of various widths, with lightly-doped drain (LDD) structures. Among all investigated TFTs, the nano-scale TFT with ten 67 nm-wide split channels (M10) has superior and more uniform electrical characteristics than other TFTs, such as a higher ON/OFF current ratio (>109), a steeper subthreshold slope (SS) of 137 mV/decade, an absence of drain-induced barrier lowering (DIBL) and a suppressed kink-effect. These results originate from the fact that the active channels of M10 TFT has best gate control due to its nano-wire channels were surrounded by tri-gate electrodes. Additionally, experimental results reveal that the electrical performance of proposed TFTs enhances with the number of channels from one to ten strips of multiple channels sequentially, yielding a profile from a single gate to tri-gate structure.
In addition, we have also studied the multi-gate combining the pattern-dependent nickel (Ni) metal-induced lateral crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with ten nanowire channels. Experimental results reveal that applying ten nanowire channels improves the performance of Ni-MILC poly-Si TFT, which thus has a higher ON current, a lower leakage current and a lower threshold voltage (Vth) than single-channel TFTs. Furthermore, the experimental results reveal that combining the multi-gate structure and ten nanowire channels further enhances the entire performance of Ni-MILC TFTs, which thus have a low leakage current, a high ON/OFF ratio, a low Vth, a steep subthreshold swing (SS) and kink-free output characteristics. The multi-gate with ten nanowire channels NI-MILC TFTs has few poly-Si grain boundary defects, a low lateral electrical field and a gate channel shortening effect, all of which are associated with such high-performance characteristics. The PDMILC TFTs process is compatible with CMOS technology, and involves no extra mask. Such high performance PDMILC TFTs are thus promising for use in future high-performance poly-Si TFT applications, especially in AMLCD and 3D MOSFET stacked circuits.
Otherwise, we have investigated the mechanism of the leakage currents in polysilicon TFT with different temperature and applied biases. Moreover, we have simulated the electric fields in different structure polysilicon TFT to explain the mechanism of the leakage currents. By comparing the leakage currents in different channel structures, the leakage current in nanowire channel structure is higher than that in non-nanowire channel structure. Moreover, the leakage current in multiple gate structure is lower than that in single gate structure. Therefore, these two experimental results are caused by high electric field in the drain-to-gate overlap and drain-to-body depletion region respectively.

Chapter 1 Introduction
1.1 Overview of polysilicon thin-film transistor technology 1
1.2 Motivation 6
1.3 Thesis outline 7
References

Chapter 2 Poly-Si TFT Conduction Mechanism and Poly-Si Formation Mechanism
2.1 Poly-Si TFT transportation mechanism 12
2.2 Method of device parameter extraction 16
2.3 Poly-Si TFT non-ideal effect 20
2.4 Metal-induced lateral crystallization formation mechanism 22
2.5 Solid phase crystallization formation mechanism 25
References

Chapter 3 Leakage Current in Metal-induced Lateral Crystallization Polysilicon Thin-Film Transistors with Multiple Nano-wire Channels and Multiple Gates
3.1 Introduction 38
3.2 Mechanism of leakage current in polysilicon TFT 39
3.3 Device structure, simulation, and fabrication 42
3.4 Results and discussion 44
References

Chapter 4 Leakage Current in Solid-Phase Crystallization Polysilicon Thin-Film Transistors with Multiple Nano-wire Channels
4.1 Introduction 60
4.2 Physical phenomena of GIDL 61
4.3 Devices structure and fabrication 62
4.4 Results and discussion 65
References

Chapter 5 Conclusion 86

Chapter 1
[1] Ichio Yudasaka et al. “Polysilicon Thin-Film Transistors”, Mat Res. Soc. Symp. Proc.,pp.162, vol.182, 1990.
[2] S. Wolf and R. N. Tauber, “Silicon Processing for the VLSI Era”, Lattice Press, California,vol.1, chap.6, pp.161, 1986.
[3] S. D. Brotherton, “Polycrystalline Silicon Thin Film Transistors”Semicond. Sci. Technol.,10, 1995.
[4] C. H. Fa and T. T. Jew, “The Polysilicon Insulated-Gate Field-Effect Transistors”, IEEE Trans. Electron Devices, vol.13, no.2, pp.290, 1966.
[5] G. Baccarani, B. Ricco and G. Spadin, “Transport Properties of Polycrystalline Silicon Films”, J. Appl. Phys., vol.49, pp.5565, 1978.
[6] I-Wei Wu, Alan G. Lewis, Tiao-Yuan Huang, Warren B. Jackson and Anne Chiang,“Mechanism and Device-to-Device Variation of Leakage Current in Polysilicon Thin Film Transistors”, IEDM 1990, pp.867-870.
[7] P. Migliorate, “Progress in Active Matrix Addressing of LCDs”, in Pro. Int. Display Res.Conf., pp.44, 1987.
[8] Masanori Yuki, Kunio Masumo, and Masaya Kunigita, “A Full-Color LCD Addressed byPoly-Si TFTs Fabricated Below 450℃”, IEEE Transaction on Electron Devices, vol.36,no.9, pp.1934-1937, 1989.
[9] A. G. Lewis, David D. Lee and R. H. Bruce, “Polysilicon TFT Circuit Design and Performance”, IEEE J. Solid-State Circuit, vol.27, no.12, pp.1833, 1992
[10] T. Morita, Y. Yamamoto, M. Itoh, H. Yoneda, Y. Yamane, S. Tsuchimoto, F. Funadda and K. Awane, “VGA Driving with Low Temperature Processed Poly-Si TFTs”, IEDM Tech.Dig. pp.841, 1995.
[11] M. J. Edwards, S.D. Brotherton, J. R. Ayres, D.J. McCulloch and J. P. Gowers, “Laser Crystallized Poly-Si Circuits for AMLCDs”, Asia Display, pp.335, 1995.
[12] Shunji Seki, Osamu Kogure, and Bunjiro Tsujiyama, “Effects of Crystallization on trap State Densities at Grain Boundaries in Polycrystalline Silicon”, IEEE Electron Device Lett., vol.8, pp.368-370, August 1987.
[13] T. W. Little, K. I. Takahara, H. Koike, et al, “Low Temperature Poly-Si TFTs Using Solid Phase Crystallization of Very Thin Films and an Electron Cyclotron Resonance Chemical vapor deposition gate insulator”, Jpn. J. Appl., Phys., vol.30, no.12B, pp.3724-3728,December 1991.
[14] Hiroyuki Kuriyama, Seiichi Kiyama, Shigeru Nouguchi, et al, “Enlargement of poly-Si Film Grain Size by Excimer Laser Annealing and its Application to High-Performance Poly-Si Thin Film Transistor”, Jpn. J. Appl. Phys., vol.30, no.12B, pp.3700-3703, December 1991.
[15] S. W. Lee and S.K. Joo, “Low Temperature Poly-Si Thin Film Transistors Fabrication by Metal-Induced Lateral Crystallization”, IEEE Electron Device Lett., vol.17, no4,pp.160-162, April 1996.
[16] M. K. Hatalis and D.W. Greve, “High Performance Thin Film Transistors in Low-Temperature Crystallized LPCVD Amorphous Silicon Films”, IEEE Electron Device Lett., vol.8, pp.361-364, 1987.
[17] Mingxiang Wang, Zhiguo Meng, and Man Wong, “Anisotropic Conduction Behavior in Metal-Induced Laterally Crystallized Polycrystalline Silicon Thin Films”, Appl. Phys. Lett., Vol.76, pp.448, 2000.
[18] S. D. Brotherton, D. J. McCulloch, J. P. Gowers, and A. Gill, “Laser Crystallized Poly-Si TFTs”, Microelectron. Eng., vol.19, pp.101-104, 1992.
[19] Byung-Seong Bae and Choochon Lee, “Effect of Interface State Distribution on Field Effect Conductance Activation Energy in Hydrogenated Amorphous Silicon Thin Film transistors”, J. Appl. Phys., vol.88, pp.3439-3442, 1990.
[20] M. J. Powell, J. Pritchard, “The Effect of Surface States and Fixed Charge on the Field Effect Conductance of Amorphous Silicon”, J. Appl. Phys., vol.54, pp.3244-3248, 1983.

Chapter 2
[1] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys. Vol. 53, pp.1193-1202, 1982.
[2] P. Migliorato, C. Reita, G. Tallatida, M. Quinn and G. Fortunato, “Anomalous off-current mechanisms in n-channel poly-Si thin film transistors,” Solid-State-Electronics, Vol.38, pp.2075-2079, 1995.
[3] M. Hack, I-W. Wu, T. H. King and A. G. Lewis, “Analysis of Leakage Currents in Poly-silicon Thin Film Transistors,” IEDM Tech. Dig., vol. 93, pp. 385-387, 1993.
[4] “Polycrystalline silicon for integrated circuits and displays,” second edition,
written by Ted Kamins, pp.200-210.
[5] John Y. W. Seto, ” The electrical properties of polycrystalline silicon films,“ J. Appl. Phys. Vol. 46, NO. 12, Dec.1975.
[6] Filippos V. Farmakies, and Jean Brini, George Kamarinos, Constantainos T. Angelis, and Charalambos A. Dimitriadis, “On-Current Modeling of Large-Grain Polycrystalline Silicon Thin-Film Transistors” IEEE Trans.On Electron Device, vol.48, NO.4, APRIL 2001.
[7] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys. Vol. 53, pp.1193-1202, 1982.
[8] R. E. Proano, R. S. Misage, D. G. Ast, ”Development and Electrical Properties of Undoped Polycrystalline Silicon Thin-Film Transistors.”, IEEE Electron Device Lett. Vol. 36. No. 9. pp. 1915-1922, Sept. 1989.
[9] K. R. Olasupo and M. K. Hatalis, “Leakage Current Mechanism in Sub-Micron Polysilicon Thin-Film Transistors,” IEEE Trans. Electron Devices, ” Vol. 43, pp.1218, 1996.
[10] C. T. Angelis, C. A. Dimitriadis, I. Samaras, J. Brini, G. Kamarinos, V. K. Gueorguiev, and Tz. E. Ivanov, “Study of leakage current in n-channel and p-channel polycrystalline silicon thin-film transistors by conduction and low frequency noise measurements” p. 4095-4101, J. Appl. Phys. Vol. 82 , 1997.
[11] S.M. Sze “Semiconductor Devices Physics and Technology,” second edition, , Wiley, New York, 2002.
[12] C. Hayzelden and J. L. Batstone, “Silicide formation and silicide-mediated crystallization of nickel-implanted amorphous silicon thin film,” J. Appl. Phys., vol.73, pp.8279-8289,1993.
[13] C. F. Cheng, Vincent M. C. Poon, C. W. Kok, and Mansun Chan, “Modeling of Grain Growth Mechanism by Nickel Silicide Reactive Grain Boundary Effect in Metal-Induced-Lateral-Crystallization,” IEEE Trans. Electron Devices, Vol.50, pp.1467-1474, 2003.
[14] D. Turnbull, “Beam-Solid Interactions and Phase Transformation,” Mater. Res. Soc. Symp. Proc., 51, 71, (1985)
[15] R. Kakkad, J. Smith, W. S. Lau, S. J. Fonash and R. Kerns, “Crystallized Si films by low-temperature rapid thermal annealing of amorphous silicon,” J. Appl. Phys., 65, 2069(1989)
[16] H. Y. kim, J. B. Choi, and J. Y. Lee, “Effects of silicon-hydrogen bond characteristics on the crystallization of hydrogenated amorphous silicon films prepared by plasma enhanced chemical vapor deposition ” J. Vac. Sci Technol. A, 17, 3240(1999).
[17] J. S. Lannin, L. J. Pilione, S. T. Kshirsagar, R. Messier, and R. C. Ross, “Variable structural order in amorphous silicon,” Phys. Rev. B, 26, 3506(1982)

[18] K. Nakazawa, “Recrystallization of amorphous silicon films deposited by low-pressure chemical vapor deposition from Si2H6 gas,” J. Appl. Phys., 69, 1703(1991)

Chapter 3
[1] H. Wang, M. Chan, S. Jagar, V. M. C. Poon, M. Qin, Y. Wang and P. K. Ko, “Super Thin-Film Transistor with SOI CMOS Performance Formed by a Novel Grain Enhancement Method”, IEEE Trans. Electron Devices, vol. 47, p. 1580-1586, Aug. 2000.
[2] Z. Meng, M. Wang, and M. Wong, “High Performance Low Temperature Metal-Induced Unilaterally Crystallized Polycrystalline Silicon Thin Film Transistors for System-on-Panel Applications”, IEEE Trans. Electron Devices, vol. 47, p. 404-409, Feb. 2000.
[3] T. Unagami, and O. Kogure, “Large ON/OFF Current Ratio and Low Leakage Current Poly-Si TFT’s with Multichannel Structure” IEEE Trans. Electron Devices, vol. 35, p. 1986-1989, Nov. 1988.
[4] Y. C. Wu, T. C. Chang, C. Y. Chang, C. S. Chen, C. H. Tu, P. T. Liu, H. W. Zan, and Y. H. Tai, “High-performance polycrystalline silicon thin-film transistor with multiple nanowire channels and lightly doped drain structure,” Appl. Phys. Lett., vol. 84, p. 3822-3824, 2004.
[5] C. F. Cheng, M. C. Poon, C. W. Kok, and M. Chan, “Modeling of metal-induced-lateral-crystallization mechanism for optimization of high performance thin-film-transistor fabrication”, in IEDM Tech. Dig., p. 569 – 572, 2002.
[6] S. W. Lee and S. K. Joo, “Low temperature polysilicon thin-film transistor f abricated by metal-induced lateral crystallization”, IEEE Electron Device Lett., vol. 17, p. 160-162, Apr. 1996.
[7] J. H. Park, and C. J. Kim, “A study on the fabrication of a multigate/multichannel polysilicon thin-film transistor”, Jpn. J. Appl. Phys., vol. 36, p. 1428-1432, Mar. 1997.
[8] C. T. Angelis, and C. A. Dimitriadis, “Study of leakage current in n-channel and p-channel polycrystalline silicon thin-film transistors by conduction and low frequency noise measurements”, J. Appl. Phys. 82 (8), October 1997

Chapter 4
[1] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon,Y. Taur, and H.-S. P. Wong, “Device scaling limits of Si MOSFETs and their application dependencies,” Proc. IEEE, vol. 89, pp. 259–288, Mar. 2001.
[2] J.-H. Chen, S.-C. Wong, and Y.-H. Wang, “An analytical three-terminal band-to-band tunneling model on GIDL in MOSFET,” IEEE Trans. Electron Devices, vol. 48, pp. 1400–1405, July 2001.
[3] L. Esaki, “Discovery of the tunnel diode,” IEEE Trans. Electron Devices, vol. ED-23, pp. 644–647, 1976.
[4] K. R. Kim, D. H. Kim, S.-K. Sung, J. D. Lee, and B.-G. Park, “Negative- differential transconductance characteristics at room temperature in 30-nm square-channel SOI nMOSFETs with a degenerately doped body,” IEEE Electron Device Lett., vol. 23, pp. 612–614, June 2002.
[5] J. Koga and A. Toriumi, “Three-terminal silicon surface junction tunneling device for room temperature operation,” IEEE Electron Device Lett., vol. 20, pp. 529–531, 1999.
[6] K. F. You and C. Y. Wu, “A new quasi-2-D model for hot-carrier band-to-band tunneling current,” IEEE Trans. Electron Devices, vol. 46, p. 1174, June 1999.