本論文包含兩研究主題：應用於ECG（Electrocardiogram）之高效能電流式儀表放大器與具CMRR（Common-Mode Rejection Ratio）自我校正之儀表放大器。

第一個主題探討一適用於生醫ECG訊號擷取之儀表放大器，以TSMC 0.18 μm CMOS製程實現。其增益為45 dB，共模拒斥比（Common Mode Rejection Ratio, CMRR）為127 dB，輸入參考雜訊低（Input Referred Noise）且工作頻寬範圍介於0.2-200 Hz之間。本設計為一電流式儀表放大器架構，藉由Gm-C技術完成低頻零點。其利用了一改良式運算轉導放大器（Operation Transconductance Amplifier，OTA）架構來減小原本所需要的大電容值，以降低晶片成本與面積。

第二個主題探討一可自我校正CMRR的儀表放大器，同樣以TSMC 0.18 μm CMOS製程實現。其利用一傳統式的儀表放大器，加上一可調式電阻以及一偵測電路，可修正電阻之間的匹配，藉此提高CMRR，讓其可自動校正（Self-Calibration）以達到80 dB以上的共模拒斥比。本設計的增益為60 dB，頻寬範圍小於10 KHz，適用於生醫訊號的擷取。本電路之貢獻在於讓傳統式儀表放大器減少對於電阻的依賴性，且對於不同的製程角落模擬（PVT Corner Simulation），儀表放大器最後都能達到CMRR大於80 dB的規格。

The thesis is composed of tow topics: a high performance current-balancing instrumentation amplifier (IA) for ECG (Electrocardiogram) monitoring systems and an IA with CMRR (Common-Mode Rejection Ratio) self-calibration.

In the first topic, a high common mode rejection ratio (CMRR) and a low input referred noise instrumentation amplifier (IA) is presented for ECG applications. A high pass filter (HPF) with a small-Gm OTA using a current division technique is employed to attain small transconductance, which needs only a small capacitor in the HPF such that the integration on silicon is highly feasible. The proposed design is carried out by TSMC standard 0.18 μm CMOS technology. CMRR is found to be 127 dB and the voltage gain is 45 dB according to the simulation results.

The second topic discloses an instrumentation amplifier with CMRR self-calibration capability. The propose design is also carried out by TSMC standard 0.18 μm CMOS technology. To achieve a CMRR of more than 80 dB, a calibration resistance string and a detection circuit have been utilized. The DC gain of the proposed design is 60 dB and the frequency bandwidth is bound in 10 KHz, which is adaptable for biomedical signal acquisition applications.

致謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vii
表目錄 ix
第一章 概論 1
1.1 研究動機 1
1.2 相關技術與文獻探討 2
1.2.1 習知儀表放大器 2
1.2.2 電流式儀表放大器 3
1.2.3 低頻零點 5
1.3 論文大綱 6
第二章 應用於ECG之高效能電流式儀表放大器 7
2.1 簡介 7
2.2 電路架構與設計 7
2.3 電路原理 8
2.3.1 儀表放大器初步架構說明 8
2.3.2 電路小訊號分析與共模拒斥比的推算及改進 10
2.3.3 Gm-C濾波器架構及原理分析 13
2.3.4 偏壓電路 16
2.4 電路模擬與預計規格 18
2.4.1 電路佈局後模擬結果 18
2.4.2 預計規格列表 19
2.5 晶片佈局 20
2.6 晶片實作與量測結果 21
2.6.1 晶片量測結果分析與討論 23
2.6.2 效能比較 25
2.7 結果與討論 27
第三章 具CMRR自我校正之儀表放大器 29
3.1 簡介 29
3.2 電路架構與設計 30
3.3 電路原理 31
3.3.1 前級放大器 31
3.3.2 可調式電阻（VR）電路架構原理說明 33
3.3.3 後級放大器 35
3.3.4 峰對峰偵測器 36
3.3.5 電阻自動搜尋與選擇電路（ARSFC） 38
3.3.6 時序控制器 45
3.4 電路模擬與預計規格 46
3.4.1 電路佈局後模擬結果 46
3.4.2 預計規格列表 49
3.4.3 效能比較 50
3.5 晶片佈局 51
3.6 結果與討論 52
第四章 研究成果與結論 54
參考文獻 56

[1]R. J. Baker, “Current Mirrors,” in CMOS Circuit Design, Layout and Simulation, revised second edition, New Jersey: John Wiley & Sons, Inc., 2008, chapter 20, section 20.1.3, pp. 624-630.
[2]S. Sedra, and K. C. Smith, “Difference amplifiers,” in Microelectronic Circuits, fifth edition, New York: Oxford University Press, 2004, chapter 2, section 2.4.2, pp. 85-89.
[3]H.-C. Chow, and J.-Y. Wang, “High CMRR instrumentation amplifier for biomedical applications,” in 9th International Symposium on Signal Processing and Its Applications, pp. 1-4, Feb. 2007.
[4]R. Martins, S. Selberherr, and F. A. Vaz, “A CMOS IC for portable EEG acquisition systems,” in Proc. IEEE Instrumentation and Measurement Technology Conference, vol. 2, pp. 1406-1410, May 1998.
[5]H. Krabbe, “A high-performance monolithic instrumentation amplifier,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, vol. 14, pp. 186-187, Feb. 1971.
[6]R. F. Yazicioglu, P. Merken, and C. V. Hoof, “Effect of electrode offset on the CMRR of current balancing instrumentation amplifiers,” in PhD Research in Microelectronics and Electronics, vol. 1, pp. 35-38, July 2005.
[7]P. A. Dal Fabbro, and C. A. Dos Reis Filho, “An integrated CMOS instrumentation amplifier with improved CMRR,” in Proc. 15th Symposium On Integrated Circuits and Systems Design, pp. 57-61, Sept. 2002.
[8]C. Nanda, J. Mukhopadhyay, D. Mandal, and S. Chakrabarti, “A CMOS instrumentation amplifier with low voltage and low noise for portable ECG monitoring systems,” in IEEE International Conference on Semiconductor Electronics, pp. 54-58, Nov. 2008.
[9]J. Silva-Martinez, and S. Solis-Bustos, “Design considerations for high performance very low frequency filters,” in Proc. IEEE International Symposium on Circuits and Systems, vol. 2, pp. 648-651, July 1999.
[10]M. Shojaei-Baghini, R. K. Lal, and D. K. Sharma, “An ultra low-power CMOS instrumentation amplifier for biomedical applications,” in IEEE International Workshop on Biomedical Circuits and Systems, pp. 1-4, Dec. 2004.
[11]T. Denison, K. Consoer, W. Santa, A.-T. Avestruz, J. Cooley, and A. Kelly, “A 2 μW 100 nV/rtHz chopper-stabilized instrumentation amplifier for chronic measurement of neural field potentials,” IEEE Journal of Solid-State Circuits, vol. 42, no. 12, pp. 2934-2945, Dec. 2007.
[12]K.-A. Ng, and P.-K. Chan, “A CMOS analog front-end IC for portable EEG/ECG monitoring applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 11, pp. 2335-2347, Nov. 2005.
[13]C.-C. Huang, S.-H. Hung, J.-F. Chung, L.-D. Van, and C.-T. Lin, “Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition,” in IEEE International Symposium on Circuits and Systems, pp. 2717-2720, May 2008.
[14]C.-H. Hsu, C.-C. Huang, K.-S. Lim, W.-C. Hsiao, and C.-C. Wang, “A high performance current-balancing instrumentation amplifier for ECG monitoring systems,” in International SOC Design Conference, pp. 83-86, Nov. 2009.
[15]M. Shojaei-Baghini, R. K. Lal, and D. K. Sharma, “A low-power and compact analog CMOS processing chip for portable ECG recorders,” in Asian Solid-State Circuits Conference, pp. 473-476, Nov. 2005.
[16]H. Wu, and Y.-P. Xu, “A low-voltage low-noise CMOS instrumentation amplifier for portable medical monitoring systems,” in The 3rd International IEEE-NEWCAS Conference, pp. 295-298, June 2005.
[17]C. Nanda, J. Mukhopadhyay, D. Mandal, and S. Chakrabarti, “1 V CMOS instrumentation amplifier with high DC electrode offset cancellation for ECG acquisition systems,” in IEEE Students’ Technology Symposium (TechSym), pp. 21-25, April 2010.
[18]J.-S. Liou, “A low-noise instrumentation amplifier for neural signal sensing and a low-power implantable bladder pressure monitor system,” M.S Thesis, Graduate Division in Dept. of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan, June 2007.
[19]N. V. Helleputte, J. M. Tomasik, W. Galjan, A. Moro-Sanchez, D. Schroeder, W. H. Krautschneider, and R. Puers, “A flexible system-on-chip (SOC) for biomedical signal acquisition and processing,” ELSEVIER Sensors and Actuators A: Physical, vol. 142, no. 1, pp. 361-368, March 2008.
[20]K. M. Hafkemeyer, W. Galjan, J. M. Tomasik, D. Schroeder, and W. H. Krautschneider, “System-on-chip approach for biomedical signal acquisition,” in Proc. ProRISC, pp. 26-29, Nov. 2007.
[21]C. Bronskowski, and D. Schroeder, “A programmable analog front end for the aquisition of biomedical signals,” in Proc. ProRISC, pp. 474-477, Nov. 2004.
[22]W. Galjan, K. M. Hafkemeyer, J. M. Tomasik, F. Wagner, W. H. Krautschneider, and D. Schroeder, “Highly sensitive biomedical amplifier with CMRR calibration and DC-offset compensation,” in IEEE EUROCON, pp. 152-155, May 2009.
[23]C.-C. Huang, “Linear LDO regulator with modified NMCF frequency compensation and low noise amplifier for neural signal sensing and recording,” M.S Thesis, Graduate Division in Dept. of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan, June 2004.