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博碩士論文 etd-0719111-224316 詳細資訊
Title page for etd-0719111-224316
論文名稱
Title
短路連通柱於多層印刷電路板之最佳化配置研究與分析
Analysis of the Optimal Distribution of Shorting Vias in Multi-Layer Printed Circuit Board
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
83
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2011-07-18
繳交日期
Date of Submission
2011-07-19
關鍵字
Keywords
瞬時切換雜訊、設計法則、空腔模型、保型時域有限差分法、短路連通柱
Cavity Model, Design Rule, Simultaneous Switching Noise, Conformal Finite-Difference Time Domain, Shorting Via
統計
Statistics
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中文摘要
在現代化的高速數位電路中,傳統的單層或雙層電路板在運用空間上已不敷使用,電路的多層化及堆疊式分佈技術將更為普遍,而各個訊號層間垂直方向的聯繫通道稱之為穿孔結構(Via),由於此結構必須穿過電源層及接地層間形成的平行板空腔,將會受到嚴重的瞬時切換雜訊(Simultaneous Switching Noise)干擾,如何將此雜訊的傷害降到最小,是重要的課題。

在多層印刷電路板中,短路連通柱(Shorting Via)是將相同極性的電源層或接地層連接的結構,於本論文中主要探討此短路連通柱的擺放位置對於電源分佈網路內空腔模態的影響,並提出一套連通柱的擺置規則能夠有效降低瞬時切換雜訊,對於多層電路板之電源完整性有顯著的幫助。
Abstract
In modern high-speed digital circuits, the space of the traditional single-layered or double-layered circuit board is not enough, therefore multi-layered circuit and stacked distribution technology are widely applied to many applications. The signal via is a vertical interconnection structure to communicate different signal layers, which will be seriously interfere with the simultaneous switching noise by via through the parallel plate cavity that consists of power and ground plane. It is an important issue to minimize the influence from noise.

In multi-layered printed circuit boards, shorting vias are usually utilized to interconnect the planes with the same voltage level. The major theme of this thesis is the placement of shorting vias affecting plane cavity mode. And we propose a design rule of the shorting vias to significantly decrease the simultaneous switching noise and improve the power integrity of multi-layered circuit board.
目次 Table of Contents
論文審定書…………………………………………………………………………….i
誌謝……………………………………………………………………………………ii
中文摘要……………………………………………………………………………...iii
英文摘要……………………………………………………………………………...iv
第一章 序論…………………………………………………………………………1
1.1 研究背景與目的…………………………………………………………….1
1.2 文獻回顧與探討…………………………………………………………….2
1.3 研究與貢獻………………………………………………………………….4
1.4 論文大綱…………………………………………………………………….4
第二章 瞬時切換雜訊………………………………………………………………6
2.1 瞬時切換雜訊成因………………………………………………………….6
2.2 印刷電路板之共振現象…………………………………………………….7
2.3 常見的抑制瞬時切換雜訊方法…………………………………………….9
2.3.1 使用去耦合電容抑制瞬時切換雜訊………...…………………………..9
2.3.2 使用孤立電源島與短路連通柱抑制瞬時切換雜訊……….……………10
2.3.3 使用電磁能隙結構抑制瞬時切換雜訊………………….……………..13
第三章 短路連通柱擺置之最佳化………………………………………………..16
3.1 短路連通柱對動力面共振模態影響………………………………………16
3.2 使用空腔模型解析動力面之阻抗參數……………………………………19
3.2.1 空腔模型……………………………………...………………………...19
3.2.2 由空腔模型解釋其模態抑制技巧…………...………………………...21
3.2.3 不規則形狀結構的阻抗模型………………...………………………...22
3.2.4 使用空腔模型模擬多層板與短路連通柱結構……...………………...27
3.3 短路連通柱之最佳化配置研究……………………………………………32

3.3.1 最佳配置與寄生模態頻率關係探討………...………………………...32
3.3.2 是否為最佳配置之驗證……………………...………………………...36
3.3.3 寄生共振頻率的估算……...………...…………………………………39
3.3.4 此設計法則與經驗法則的比較………...……………………………...43
3.4 其它結構變化對於寄生共振模態頻率的影響……………………………44
第四章 動力面對訊號過孔結構的雜訊耦合與抑制機制………………..………50
4.1 時域有限差分法原理及保角型修正時域有限差分法……………………50
4.1.1 時域有限差分法原理概要……...…………...…………………………50
4.1.2 加入保角修正型之時域有限差分法……...………..………………….53
4.2 於多層板中使用多個短路連通柱對訊號連通柱的雜訊抑制……………56
4.3 使用平面型電磁能隙結構與短路連通柱結合之雜訊抑制效果…………62
第五章 結論………………………………………………………………………..68
參考文獻……………………………………………………………………………..69
參考文獻 References
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