為應付現今多變的程式與不同性質的工作量，多核心處理器的設計已是目前一大課題，而非對稱性多核心處理器(Asymmetric Multicore Processors, AMPs)即是因應這些需求而產生的設計。超多純量(Hyper-scalar)微處理器系統架構，為非常具有彈性應用的非對稱性多核心處理器架構，該架構在執行同一執行緒程式時，因指令分析器的指令間相依性分析，核心間可經由虛擬共享暫存器進行資料交互傳輸以達到多核心共同加速單一執行緒效能。在超多純量架構下，處理器核心為了同時作到可單獨執行單一執行緒，與多核心間共同加速單一執行緒，提出可亂序執行並依序寫回的處理器核心單元架構。本論文為實現適用於超多純量架構之處理器核心單元，此核心單元加入了兩個資料處理階段，使核心具有資料處理中心可支援亂序執行依序寫回的功能，同時考量記憶體讀寫之順序及跳躍指令的調整已符合程式的運作。
處理器單元為適用於超多純量處理器的架構，依照指令運行機制主可分為三個部分討論並實現：一、指令流：增加資料處理中心與指令序號表、暫存器來源資料表的指令資訊交流，達到可亂序執行指令，依序完成指令之功能需求；二、記憶體存取規則：透過記憶體單元的設計，實現記憶體讀寫指令在亂序執行條件下依然保持正確的順序；三、跳躍指令依序執行：在亂序執行條件下，跳躍指令需保存運算結果，直到依序完成執行時才可進行跳躍指令。
論文最後我們利用撰寫Verilog與FPGA合成電路評估模擬與測試，確定此核心單元在執行指令時可適於超多純量架構所要求的指令流控制、記憶體讀寫管理及跳躍指令的正確執行，未來可以此核心單元建構出雙核心、四核心等多核心超多純量處理器架構。

To meet the needs of a diverse range of programs and workloads, the design of multi-core processors is a major issue. Asymmetric multi-core processors (AMPs) design have been generated to the demand. The hyper-scalar microprocessor system architecture, which a kind of asymmetric multi-core processors with highly flexible applications. To achieve the increase of single thread performance in multi-core jointly execute, this architecture allows Virtual Shared Register Files (VSRF) to exchange data information within cores with the analysis of Instruction Analyzer (IA) when performs the same thread programs. In order to perform executing single-thread programs independently and accelerating single-thread programs within cores simultaneously, the hyper-scalar architecture propose core elements with out-of-order execution and in-order commit. This paper propose to implement a core element for hyper-scalar architecture. We puts in two data processing stage so that the core element support out-of-order execution and in-order commit with data processing unit. In addition, we benefit the programs with both considering the order of memory access and the adjustment of branch instruction.
To applicable the hyper-scalar processor architecture, we discuss and implement the instruction operation mechanism, which can be section into three: First, Instruction Flow: To get up to the demands of out-of-order execution and in-order commit instructions, we add the data processing unit, instruction sequence table and register source table to the pipeline. Second, Memory Access Flow: Implementation of maintaining the correct order of memory access under the out-of-order execution by design of the memory unit. Third, Branch Ordered Flow: The computation of branch instructions should be saved until the instruction is completed in turn under the out-of-order execution.
Finally we evaluate the result of simulation and testing through Verilog language and FPGA circuit synthesis. The result prove that the core element is applicable for the hyper-scalar claims of instruction flow control, memory access management and correct branch instruction execution. We can construct the two-core, four-core, or even multi-core hyper-scalar processors by the core element in the future.

論文審定書 i
論文公開授權書 ii
致謝 iii
摘要 iv
Abstract v
目錄 vii
圖次 xi
表次 xiv
第一章 緒論 1
1.1 研究動機 1
1.2 研究目的 2
1.3 論文架構 3
第二章 背景知識與相關研究 4
2.1 現今非對稱多核心處理器(AMPs)設計分類 4
2.2 WiDGET(Wisconsin Decoupled Grid Execution Tiles) 6
2.2.1 Pipeline Stage 7
2.2.2 Front-end 7
2.2.3 Execution Unit 9
2.3 Bahurupi 9
2.3.1 Bahurupi Architecture 10
2.3.2 Bahurupi Execution model 11
2.3.3 Bahurupi Architecture details 13
2.4 超多純量(Hyper-scalar)架構介紹 15
2.4.1 指令分析器 18
2.4.2 虛擬共享暫存器檔案 20
2.5 可動態分配核心處理器架構特色功能整理 22
第三章 實現適用於超多純量架構之核心單元 24
3.1 超多純量處理器核心單元指令運行機制 25
3.1.1 Instruction Flow 26
3.1.2 Memory Access Flow 30
3.1.3 Branch Ordered Flow 30
3.2 Instruction Flow之實現 31
3.2.1 Pre-decoder 與 Fetch stage 31
3.2.2 Decoder stage 32
3.2.3 Data stage 34
3.2.4 Execution stage 36
3.2.5 Commit stage 38
3.2.6 Writeback stage 39
3.2.7 暫存器來源資料表(Register Source Table) 39
3.2.8 指令序號表(Sequence table) 41
3.3 Memory Access Flow之實現 42
3.3.1 Memory stage 42
3.3.2 Decoder stage、Execution stage、指令序號表、Commit stage 43
3.4 Branch Ordered Flow之實現 44
3.4.1 Commit跳躍指令執行 45
3.4.2 Pre-decoder與Fetch跳躍指令執行 46
3.5 核心單元整體架構 46
3.5.1 Fetch stage 47
3.5.2 Decoder stage 47
3.5.3 Data stage 48
3.5.4 Execution stage 49
3.5.5 Memory stage 49
3.5.6 Commit stage 50
3.5.7 Writeback stage 51
第四章 模擬與驗證 52
4.1 處理器核心單元合成結果 52
4.2 處理器核心單元指令運行模擬分析 53
4.2.1 Instruction Flow與Branch Ordered Flow模擬分析 54
4.2.2 Memory Access Flow模擬分析 57
4.2.3 指令模擬測試結果分析 59
4.3 雙核心架構之指令模擬驗證 59
4.3.1 奇數和偶數和指令模擬驗證 60
4.3.2 矩陣相乘指令模擬 61
4.3.3 指令模擬驗證比較 63
第五章 結論 65
參考文獻 66

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