在本論文中，顯示平面結構的多晶矽無接面薄膜電晶體在通道厚度極薄，約為1.5 nm並施加較大汲極電壓時，可以表現出次臨界擺幅小於60 mV/dec.的現象。不同於一般多晶矽無接面薄膜電晶體，本篇元件為隨汲極電壓增大，臨界電壓有正向偏移的異常行為，且在較大汲極電壓可以提取較小的次臨界擺幅。在汲極電壓為3.0V時可以得到次臨界擺幅最小值約為30 mV/dec.，這是目前文獻中的最低紀錄，而此現象歸因於在關閉狀態時汲極側邊的高橫向電場導致的碰撞游離效應；而橫向電場隨通道厚度的減小而增加，因此當通道厚度較薄時，碰撞游離效應更加顯著。
除此之外，也討論多晶矽無接面薄膜電晶體的短通道效應，隨著通道長度的減小，臨界電壓也隨之減小且次臨界擺幅劣化。對於通道長度較短之元件，並不會發生碰撞游離效應，無法獲得次臨界擺幅低於60 mV/dec.。無論通道長度較長或較短，元件的短通道各項參數似乎因為通道厚度太薄且受到量子效應的關係，並沒有明顯改變。本論文為多晶矽無接面薄膜電晶體提出了一個新的概念，有助於無接面電晶體的發展以及未來在面板產品與3D積體電路的應用。

In this thesis, a polycrystalline silicon junctionless thin film transistor (Poly-JLTFT) with a planar structure exhibits a subthreshold swing (S.S.) of less than 60 mV/dec. when the channel thickness is extremely thin, about 1.5 nm, and a large drain voltage is applied. Different from the general Poly-JLTFT, this device is an abnormal behavior in which the threshold voltage has a positive shift as the voltage of the drain increases, and a smaller subthreshold swing can be extracted at a larger drain voltage. The minimum of the subthreshold swing (S.S.min) is about 30 mV/dec. when the drain voltage is 3.0V, which is the lowest record in the current literature. This phenomenon is attributed to the impact ionization caused by the high lateral electric field at the drain side at off-state. The lateral electric field increases as the thickness of the channel decreases, so the impact ionization effect is more pronounced when the channel thickness is thinner.
In addition, the short channel effect of the Poly-JLTFT is also discussed. As the channel length decreases, the threshold voltage also decreases and the S.S. degrades. For devices with short channel lengths, impact ionization does not occur and S.S. below 60 mV/dec. are not available. The electrical parameters of Poly-JLTFT with thinner channel thickness show similar length dependent effect to the deivce with thicker channel film. It may due to the quantum effect of ultra-thin channel film.
This work presents a new concept for polycrystalline silicon junctionless thin film transistors, which contributes to the development of junctionless transistors and future applications in panel products and 3D integrated circuits.

論文審定書 i
論文公開授權書 ii
致謝 iii
摘要 iv
Abstract v
目錄 vi
第一章 緒論與介紹 1
1.1 前言 1
1.2 薄膜電晶體 (Thin Film Transistor, TFT) 1
1.2.1 固態矽 (Type of Solids) 2
1.2.2 多晶矽薄膜電晶體(Poly-Si Thin Film Transistor, Poly-Si TFT) 2
1.3 短通道效應 (Short Channel Effect) 4
1.3.1 臨界電壓滾降 (Threshold Voltage Roll-Off) 4
1.3.2 汲極引致能障降低 (Drain-induced Barrier Lowing, DIBL) 4
1.3.3 擊穿崩潰 (Punch Through) 5
1.4 無接面電晶體 (Junctionless Transistor, JLT) 5
1.4.1 無接面電晶體 (Junctionless Transistor) 5
1.4.2 結構比較 (Structural comparison) 6
1.4.3 操作機制 (Operating Modes) 6
第二章 實驗步驟與流程 18
2.1 元件製程 18
2.2 電性參數萃取 19
2.2.1 臨界電壓 (Threshold Voltage, VTH ) 19
2.2.2 次臨界擺幅 (Subthreshold Swing, S.S.) 20
2.2.3 開啟與關閉電流比值(On and Off-State Current Ratio) 20
第三章 結果與討論 27
3.1 多晶矽無接面電晶體之通道薄化 27
3.2 多晶矽無接面電晶體之不同通道厚度之電性分析 27
3.3 多晶矽無接面電晶體之碰撞游離效應 27
3.4 多晶矽無接面電晶體之短通道效應 28
第四章 結論與未來展望 48
參考文獻 49

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