Responsive image
博碩士論文 etd-0720101-205542 詳細資訊
Title page for etd-0720101-205542
論文名稱
Title
矽島隔離部分空乏之多邊閘極SOI金氧半場效電晶體特性
Characterization of Multi-Gate Partially-Depleted SOI MOSFET with MESA Isolation
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
45
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2001-06-28
繳交日期
Date of Submission
2001-07-20
關鍵字
Keywords
部分空乏、矽在絕緣層上、逆窄通道效應、圓角化、多重閘極金氧半場效電晶體、矽島隔離
SOI, Partially Depleted, Multi-gate MOSFET, Rounded Corner, MESA Isolation, INCE
統計
Statistics
本論文已被瀏覽 5801 次,被下載 0
The thesis/dissertation has been browsed 5801 times, has been downloaded 0 times.
中文摘要
摘要
在本論文中,我們製作出一種部分空乏式多重閘極的SOI元件,並且研究探討這種元件的逆窄通道效應(INCE)。
在部分空乏式多重閘極SOI元件的結構中,是在矽島(Silicon MESA Island)上形成三面閘極,這種結構可以提昇元件的性能。然而為了消除矽島邊角(Corner)上的異常漏電流,所以使用圓角化(Rounded Corner)製程。而為了克服浮接基體效應(Floating Body Effect),我們使用蕭特基基體接出(Schottky Body Contact)。根據DAVINCI三維元件模擬及量測的結果,部分空乏式多重閘極SOI元件展示出優越的特性:低臨限電壓、低次臨界斜率與高崩潰電壓。此外,比較多重閘極元件與傳統元件的電流後,可以發現多重閘極元件有著額外的電流增益。
為了深入了解部分空乏式多重閘極SOI元件中的逆窄通道效應之行為,我們使用重疊空乏區(Overlap of depletion region)的概念導出臨限電壓偏移的表示式。然因為元件已經過圓角化製程,我們亦研究其模型公式在元件圓角化後之效應。在與實驗值比較之後,計算結果與實驗結果顯示出一致性。
Abstract
Abstract
In this thesis, a Multi-gate PD SOI Device is realized. The inverse narrow channel effect of the device is also studied.
In the Multi-gate PD SOI structure, it has three-surface gate on the silicon MESA Island, which can promote the device performance. However, for eliminating the abnormal corner leakage current in the MESA Island, the process of rounded corner is used. In order to overcome the floating body effect, we use the Schottky body contact. According to the 3-D DAVINCI device simulation and the measurement results, the Multi-gate PD SOI device presents the excellent characteristics: low threshold voltage, low subthreshold factor and high breakdown voltage. In addition, comparing the Multi-gate device with that of the conventional one, the excess drain current gain is observed.
In order to understand the behavior of INCE in Multi-gate PD SOI Device in depth, we use the concept of overlap depletion region to derive the expressions of threshold voltage shift. Owing to the device has rounded corner, we also study the rounded corner effect in the model formulation. Comparing calculation with that of the experiment one, the calculation shows agreement with the experiments.
目次 Table of Contents
Table of contents
Chapter 1 Introduction 1
Chapter 2 Multi-Gate SOI structure Developments 3
2-1 multi-gate SOI structure development 3
2-2 The 3-surface Multi-Gate PD SOI structure 8
2-3 Summary 11
Chapter 3 Simulation of Characteristics in Multi-Gate PD SOI Device 12
3-1 Multi-gate PD SOI device 12
3-2 I-V characteristics 14
3-3 The Excess Current Gain in Multi-gate PD SOI MOSFET 17
3-4 Summary 20
Chapter 4 The inverse narrow channel effect in Multi-Gate PD SOI MOSFET 21
4-1 Width variation in Multi-Gate PD SOI MOSFET 21
4-2 The expression of inverse narrow effect 24
4-3 Simulations result and discuss 27
4-4 Summary 32
Chapter 5 Experiment and Results 33
5-1 Device Fabrication 33
5-2 Device I-V characteristic 36
5-3 The Excess Current gain 39
5-4 Discussion 40
5-5 Summary 44
Chapter 6 Conclusion 45
Reference
參考文獻 References
Reference:
[1] Chenming Hu, “SOI and Device Scaling,” Proceedings 1998 IEEE International SOI Conference, Oct. 1998.
[2] S. Christoloveanu, and G. Reichert, “Recent Advances in SOI Materials and Device Technologies for High Temperature,” IEEE Transacition on Electron Devices, P.86-93, 1998.
[3] G. C. Messenger and M. S Ash, “The Effects of Radiation Electronic System,” Van Nostrand Reinhold Company, New york, P.307, 1986.
[4] Jean-Pieere Coling, “silicon-On-Isolator Technology: Materials to VLSI,” Kluwer Academic Publishers, P.107- 108.
[5] R. R. Troutman, “Latchup in CMOS Technology”, Kluwer Academic Publishers, 1986.
[6] P. S. Jue, J. T. Lin, “Study and Simulation on a New SOI Device with High Transconductance,” Master thesis, NSYSU, Taiwan, P19-33, 1998.
[7] Y. Y. Hsu, J. T. Lin, “The Study on characteristics a 3-wide SOI MOSFET,” Master thesis, NSYSU, Taiwan, P28-33, 1999.
[8] F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhance performance,” IEEE Electron Device Letters, Vol. 8, P.410- 412, 1987.
[9] S. Matsuda, T. Sato, H. Yoshimura, “Novel Corner Rounding Process for Shallow Trench Isolation utilizing MSTS (Micro-Structure Transformation of Silicon),” IEDM, P.137-140, 1998.
[10] Jeffrey Sleight, Kaizad Mistry, “A Compact Schottky Body Contact Technology for SOI Transistors,” IEDM, P.419-422, 1997.
[11] Jeffrey Sleight, Kaizad Mistry, “DC and Transient Characterization of a Compact Schottky Body Contact Technology for SOI Transistors,” IEEE Transacitions on Electron Device, Vol. 46, No. 7, P.1451-1456, July 1999.
[12] Kunihiro Suzuki, Tetsu Tanaka, Yoshiharu, Hiroshi Horie, and Yoshihiro Arimoto, “Scaling Theory for Double-Gate SOI MOSFET’s,” IEEE Transacitions on Electron Device, Vol. 40, No. 12, P.2329-2329, December 1993.
[13] Bogdan Majkusiak, Tomasz Janik, and Jakub Walczak, “Semiconductor Thickness Effects in the Double-Gate SOI MOSFET,” IEEE Transacitions on Electron Device. Vol. 45, No. 5, P.1127-1134, May 1998.
[14] Emil Arnold, “Double-Charge-Sheet Model for Thin Silicon-on-Insulator Films,” IEEE Transacitions on Electron Devices. Vol. 43, No. 12, P.2153-2163, December 1996.
[15] A. Vandooren, S. Cristoloveanu, and J. P. Colinge, “Hall Mobility Measurement in Double-Gate SOI MOSFET,” IEEE International SOI Conference, P.118-119, Oct. 2000.
[16] Jean-Pieere Coling, M. H. Gao, A. Romano-Rodríguez, “SILICON-ON-INSULATOR “GATE-ALL-AROUND DEVICE,” IEDM, P.595-598, 1995.
[17] J. P. Colinge, X. Baie, and V. Bayot, “Evidence of Two-Dimensional Carrier Confinement in Thin n-Channel SOI Gate-All-Around (GAA) Device,” IEEE Electron Device Letters, Vol. 15, No. 6, P.193-195, June 1994.
[18] Victor. W. C. Chan and Philip C. H. Chan, “Fabrication of Gate-All-Around Transistors Using Metal Induced Lateral Crystallization,” IEEE Electron Device Letters, Vol. 22, No. 2, P.80-82, February 2001.
[19] Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda, “Impact of the Vertical SOI “DELTA” Structure on Planar Device Technology,” IEEE Transacitions on Electron Device, Vol. 38, No. 6, P.1419-1424, June 1991.
[20] H. Wang, M. Chan, “The Behavior of Narrow-width SOI MOSFET’s with MESA Isolation,” IEEE Transacitions on Electron Devices. Vol. 47, No. 3, P.593-600, March 2000.
[21] Samuel K. H. Fung, “Impact of Scaling Silicon Film Thickness and Channel Width on SOI MOSFET with Reoxidized MESA Isolation,” IEEE Transacitions on Electron Devices. Vol. 45, No. 5, P.1105-1110, May 1998.
[22] B. Davari, R. H. Dennard, and G. G. Shahidi, “CMOS Scaling for High Performance and Low Power-The Next Ten Years,” IEEE Proc., Vol. 83, No 4, P.595-606, Apr. 1995.
[23] Mike S. L. Lee, Bernard M. Tenbroek, “A Physically Based Compact Model of Partially Depleted SOI MOSFET for Analog Circuit Simulation,” IEEE Journal of Solid-State Circuit, Vol. 36, No 1, P.110-121, January 2001.
[24] Jongoh Kim, Taewoo Kim, Jaebrom Park, Woojin Kim, Byungseop Hong, and Gyuhan Yoon, “A shollow Trench Isolation Using Nitric Oxide (NO)-Annealed Wall Oxide to Suppress Inverse Narrow Width Effect,” IEEE Electron Device Letters, Vol. 21, No. 12, P.575-577, December 2000.
[25] J. B. Kuo, Y. G. Chen, “Sidewall-Related Narrow Channel Effect in Mesa-Isolated Fully-Depleted Ultra-Thin SOI NMOS Device,” IEEE Electron Device Letters, Vol. 16, No. 9, P.379-381, September 1995.
[26] Samuel K. H. Fung, Mansun Chan, and Ping K. Ko, “Impact of Scaling Silicon Film Thickness and Channel Width on SOI MOSFET with Reoxidized MESA Isolation,” IEEE Transacitions on Electron Devices, Vol. 45, No. 5, P.1105-1110, May 1998.
[27] Bhavna Agrawal, Vivek K. De, and James. D. Meindl, “Three-Dimensional Analytical Subthreshold Models for Bulk MOSFET’s,” IEEE Transacitions on Electron Devices, Vol. 42, No. 12, P.2170-2180, May 1995.
[28] Kelvin Kuey-Lung Hsueh, Julian J. Sanchez, Thomas A. Demassa, and Lex A. Akers, “Inverse-Narrow-Width Effects and Small-Geometry MOSFET Threshold Voltage Model,” IEEE Transacitions on Electron Devices, Vol. 35, No. 3, P.325-338, March 1988.
[29] Chun-Yen Chang, Sun-Jay Chang, Tien-Sheng Chao, Sung-Dtr Wu, and Tiao-Yuan Huang, “Reduced Reverse Narrow Channel Effect in Thin SOI nMOSFETs,” IEEE Electron Dvice Letters, Vol. 21, No. 9, P.460-462, September 2000.
[30] Mishel Matloublan, Ravishankar Sundaresan, and Hsindao Lu, “Measurement and Modeling of the Sidewall Threshold Voltage of Mesa-Isolated SOI MOSFET’s,” IEEE Transacitions on Electron Devices, Vol. 36, No. 5, P.938-942, May 1989.
[31] Steve Shao-Shiun Chung, and Tung-Chi Li, “An Analytical Threshold-Voltage Model of Trench-Isolated MOS Device with Nonuniformly Doped Substrates,” IEEE Transacitions on Electron Devices, Vol. 39, No. 3, P.614-622, March 1992.
[32] Donald A. Neamen, “Semiconductor Physics and Device, 2nd ed.” IRWIN, P.504-507.

電子全文 Fulltext
本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。
論文使用權限 Thesis access permission:校內校外均不公開 not available
開放時間 Available:
校內 Campus:永不公開 not available
校外 Off-campus:永不公開 not available

您的 IP(校外) 位址是 3.144.42.196
論文開放下載的時間是 校外不公開

Your IP address is 3.144.42.196
This thesis will be available to you on Indicate off-campus access is not available.

紙本論文 Printed copies
紙本論文的公開資訊在102學年度以後相對較為完整。如果需要查詢101學年度以前的紙本論文公開資訊,請聯繫圖資處紙本論文服務櫃台。如有不便之處敬請見諒。
開放時間 available 已公開 available

QR Code