本篇論文架構在OFDM系統中，設計傅立葉轉換器。我們提出一個記憶體表排序刪減法，針對傅立葉轉換器硬體中存放旋轉因子(Twiddle Factor)的參數表記憶體做改善，使得存放參數表的記憶體能夠縮減，並使用處理速度較快的混合式傅立葉演算法配合單一路徑延遲回朔(Single-path Delay Feedback)的管線式架構來完成硬體設計，並透過系統模擬決定硬體設計中的訊號位元數，再依照模擬結果設計出符合OFDM系統架構且兼具省面積的傅立葉轉換器。

In this thesis, an FFT (Fast Fourier Transform) hardware circuit is designed for OFDM systems. A new memory table permutation deletion method, which can reduce the size of memory storing twiddle factors table, is proposed. The architecture of the FFT circuit is based on the faster split-radix algorithm with SDF (Single-path Delay Feedback) pipeline structure. The bits number of the signal is carefully selected by system simulation to meet the system requirements. Based on the simulation results, a small area FFT circuit is carried out for OFDM systems.

摘要 i
Abstract ii
目錄 iii
圖目錄 v
表目錄 viii
第一章 簡介 1
1.1 研究動機 1
1.2 各章摘要 2
第二章 快速傅立葉轉換(FFT) 3
2.1 分時演算法-傅立葉轉換(DIT FFT) 3
2.2 分頻演算法-傅立葉轉換(DIF FFT) 8
2.3 快速傅立葉轉換演算法架構 12
2.3.1. Radix-4 演算法 12
2.4 分割式傅立葉演算法 15
2.4.1. Radix-2/4 演算法 [4、5、6] 16
2.4.2. Radix-2/8 演算法 18
2.4.3. Radix-2/4/8 演算法 21
2.5 旋轉因子(TWIDDLE FACTOR) 23
2.6 不同RADIX演算法比較 23
第三章 管線式設計 25
3.1 多路徑延遲換向器(MDC ) 26
3.1.1. Radix-2 MDC ( R2MDC ) 26
3.1.2. Radix-4 MDC ( R4MDC ) 28
3.2 單一路徑延遲回朔(SDF) 30
3.2.1. Radix-2 SDF ( R2SDF ) 30
3.2.2. Radix-4 SDF ( R4SDF ) 32
3.2.3. Radix-2/4/8 SDF ( R248SDF ) 33
3.3 單一路徑延遲換向器(SDC) 35
3.4 各種管線架構下的硬體需求比較 36
第四章 FFT 電路設計 38
4.1 8192點RADIX-2/4/8 SDF架構 38
4.2 旋轉因子記憶體表排序刪減法 46
4.2.1. 記憶體參數表 46
4.2.2. 控制電路 48
第五章 系統模擬與探討 56
5.1 MATLAB模擬 57
5.2 QUARTUS II 模擬 70
第六章 結論 76
參考文獻 77

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