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博碩士論文 etd-0720106-151919 詳細資訊
Title page for etd-0720106-151919
論文名稱
Title
非晶矽薄膜電晶體的電性分析與可靠度研究
Investigation on Electrical Analysis and Reliability of Amorphous Silicon Thin Film Transistor
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
134
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2006-07-14
繳交日期
Date of Submission
2006-07-20
關鍵字
Keywords
可靠度、非晶矽、雙閘極
dual-gate, reliability, a-Si:H
統計
Statistics
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中文摘要
由於傳統的陰極射線管顯示器(CRT)已經被液晶平面顯示器所替代,隨著平面顯示器的尺寸增大,身為開關元件的非晶矽薄膜電晶體的性能、品質上的要求也越來越高。所以探討其可靠性與改善其功能成為一個相當重要的課題。
在本論文中,藉由元件尺寸的調變與Stress模式的變換,來模擬元件劣化過程,以探討元件的可靠度機制。可以得知,在AC Stress下元件的劣化程度與通道的長度是相依的,越長的通道所受到的劣化越少。
改善傳統的雙閘極電晶體構造,創作一個新式ITO背閘極的雙閘極薄膜電晶體,不僅製作流程可以融入現有的產線,而且元件的性能各方面都比傳統的電晶體優越。擁有較高的導通電流,以及較低的光漏電流。
本論文還利用雙閘極的結構來探討背通道部分,對於前通道傳導機制的影響。對背閘極做DC Stress,使得保護層與主動層介面產生缺陷。發現導通的電流依舊被維持在相同的大小,而光漏電流則被大量的抑制。
Abstract
The traditional displayer – CRT has already been substituted by liquid crystal displayer (LCD).The a-Si TFT is used to be a switch, while the size of the displayer increases, the require of the performance and quality of TFTs is more and more better. Therefore, it is very important subject to study the stability and to improve the performance of a-Si TFTs.
In this study, it simulated the process of the degradation on the TFTs by changing the sizes of TFTs and bias modes to find to stability mechanism of the TFTs. It can be known that under AC stress the degradation depends on the channel length, longer channel length with less degradation.
In order to improve the traditional dual-gate structure TFTs, it had made dual-gate TFTs with ITO back-gate, the process of the new structure TFTs are fully compatible with the conventional BCE TFT fabrication process. With dual-channel conduction, the dual-gate TFTs exhibit higher on current and lower photo leakage current performance than the conventional inverted staggered TFTs
In this study it also use the dual-gate structure to investigate how the back-channel influence the front-channel conduction. Apply DC bias on the back-gate to from defects at the interface of the active layer and passvation layer, it is found that after stress the on-current show almost the same quantities, and the photo leakage current is obvious decreased.
目次 Table of Contents
目錄
中文摘要 I
英文摘要 III
誌謝 IV
中文目錄 VI
English contents 44
Table Captions VIII
Figure Captions IX

第一章 序論
1.1 序論 1
1.2 掺雜氫的氫非晶矽 2
1.3 原子結構與電子能態密度 3
1.4 光漏電機制 6

第二章 結構
2.1 化學氣相沈積法沈積掺氫非晶矽 9
2.2 化學氣相沈積法沈積氮化矽 12
2.3 化學氣相沈積法沈積 n+ a-Si:H 14
2.4.1 背通道蝕刻薄膜電晶體 15
2.4.2 倒置交錯型雙閘極薄膜電晶體 15

第三章 設備儀器與參數粹取
3.1 設備儀器 17
3.2 量測之儀器設定 18
3.3元件參數粹取方法 19
3.3.1 測定起始電壓 19
3.3.2 測定次臨界擺幅 19
3.3.3 測定場效遷移率 20
3.4 態位密度 22

第四章 非晶矽薄膜電晶體的可靠度
4.1 引言 24
4.2 動機 25
4.3 結果與討論 27
4.3.1 通道寬度調變 27
4.3.2 通道長度調變 38
4.4 結論 30

第五章 雙閘極非晶矽薄膜電晶體特性
5.1引言 31
5.2動機 33
5.3結果與討論 34
5.4結論 37

第六章 雙閘極薄膜電晶體外加電壓實驗
6.1引言 38
6.2 動機 40
6.3 結果與討論 41
6.4 結論 43

References 117
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