在現今高速數位電路中，因數位邏輯的切換而產生的瞬間電流變化，會在電源平面間產生同步切換雜訊或接地彈跳雜訊。為了有效及準確的分析接地彈跳雜訊對電源供應系統的影響，電源層與接地層之間的阻抗是衡量電源供電系統特性的一個重要指標，在一定頻寬之內，電源阻抗必須小於目標阻抗。
而一般常見抑制SSN的作法，則是在電源與接地層之間添加去耦合電容提供低阻抗路徑而達到宣洩雜訊的效果，利用導納矩陣法可以快速且準確的分析去耦合電容在PCB上抑制接地彈跳雜訊的效果，節省了很多經驗嘗試法而耗費的時間。在考慮電容成本的情況之下，應用基因演算法求得以少量的去耦合電容抑制接地彈跳雜訊的最佳位置。
由於電容的寄生電感效應，使得去耦合電容在GHz以上便失去抑制效果，因此本人利用電磁能隙結構在高頻會產生截止帶，而阻止雜訊傳播的特性，結合去耦合電容並且應用基因演算法求得抑制接地彈跳雜訊的最佳位置。

In recent high-speed digital circuits, the simultaneous switching noise (SSN) or ground bounce noise (GBN) is induced due to the transient currents flowing between power and ground planes during the state transitions of the logic gates. In order to　analyze the effect of GBN on power delivery systems effectively and accurately, the impedance of power/ground is an important index to evaluate power delivery systems. In the operating frequency bandwidth, the power impedance must be less than the target impedance.
The typical way to suppress the SSN is adding decoupling capacitors to create a low impedance path between power and ground planes. By using the admittance matrix method, we can evaluate the effect of decoupling capacitors mounted on PCB fast and accurately reducing the time needed from the empirical or try-and-error design cycle. In order to reduce the cost of decoupling capacitors, the genetic algorithm is employed to optimize the placement of decoupling capacitors to suppress the GBN.
The decoupling capacitor are not effective in the GHz frequency range due to their inherent lead inductance. The electromagnetic bandgap(EBG) structure can produce a stopband to prevent the noise from disperseing at higher frequency. Combining decoupling capacitors with EBG structure to find the optimum placement for suppression of the SSN by using the genetic algorithm.

目錄
圖表目錄
第一章 序論1
1.1 研究背景與方法1
1.2 論文大綱3
第二章 高速數位電路之接地彈跳雜訊4
2.1接地彈跳雜訊的成因4
2.2接地彈跳雜訊的現象與影響7
2.3 目標阻抗(Target impedance)8
2.4 去耦合電容抑制接地彈跳雜訊8
2.4.1 去耦合電容特性8
2.4.2 去耦合電容的寄生元件9
第三章 導納矩陣(Admittance matrix method，AMM)與基因演算法13
3.1 導納矩陣簡介13
3.1.1導納矩陣法流程16
3.2 導納矩陣法模擬測試17
3.3 基因演算法介紹21
3.3.1 基因演算法流程21
3.3.2 基因演算法之特性26
3.3.3 簡單演算實例27
第四章 封裝系統的電源供應平面29
4.1 電源供應平面29
4.2 去耦合電容抑制雜訊30
4.3 電容容值對抑制效果的影響34
4.4 電容寄生元件對抑制效果的影響39
4.4.1 寄生電阻對去耦合電容功用的影響39
4.4.2 寄生電感對去耦合電容功用的影響41
4.5 應用基因演算法最佳化電容位置44
4.5.1 應用基因演算法計算6顆0.1 去耦合電容最佳位置44
4.5.2 應用基因演算法計算12顆0.1 去耦合電容最佳位置49
4.5.3 應用基因演算法計算0.1 與0.01 去耦合電容最佳位置53
第五章 利用電磁能隙(EBG)結構抑制接地彈跳雜訊60
5.1 電磁能隙簡介60
5.2 電磁能隙抑制接地雜訊61
5.3 結合EBG結構應用基因演算法最佳化電容位置67
第六章 結論72
參考文獻73

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