傳統的數位電路邏輯設計是以CMOS為主，但是以開關電晶體邏輯（Pass-Transistor Logic ; PTL）為主的邏輯電路設計，在面積、速度等方面，均有比CMOS電路有優異的表現。雖然開關電晶體已經可以達到良好的效能，但目前的Place&Route CAD Tool都是針對標準元件庫中的CMOS電路元件設計。所以如果用此種自動擺置拉線工具來產生開關電晶體佈局，會將原本使用開關電晶體邏輯電路的面積和速度優勢大打折扣。
此篇論文主要是實作以開關電晶體電路為主的後段佈局產生器，包括元件位置的最佳化擺置(placement)與繞線(routing)，以減少最後實體佈局的面積及繞線對整體速度/功率之影響。此外，本論文也將根據前段合成產生的PTL gate-level netlists ，自動搜尋電路中最長路徑所需的輸入，提供測試輸入給 HSPICE或Nanosim，以便在 post-layout中模擬最長路徑。
所以此篇論文不只能夠產生以PTL電路為主的佈局，還可產生在模擬電路時的測試pattern。

Conventional logic circuit designs are based on fully complementary CMOS logic circuits. In the past decade, many Pass-Transistor Logic (PTL) circuits have been proposed that are claimed to have better performance in area, speed and power. Most current PTL logic circuits are composed of a limited number of basic PTL cells (say 2 to 5 types of cells only). However, current placement-and-routing (P&R) CAD tools are mainly designed based on CMOS cell library which usually contains many cells with different logic functions. Thus the P&R tool does not fully exploit the features of the synthesized PTL gate-level netlists. In this thesis, we present a P&R tool dedicated to the generation of the final physical layout for the PTL netlists that are generated from a PTL synthesizer. This backend tool considers the efficient placement and routing of the PTL cells in order to reduce the area cost and to reduce the impact of the interconnection wirings on speed and power performances. Besides, in this thesis, the critical paths of the PTL netlists will be identified and the corresponding input patterns to activate these critical paths will be generated for post-layout speed simulation using HSPICE or Nanosim. In summary, the layout generator in this thesis performs the P&R of PTL netlists and also automatically find the critical paths and their corresponding input patterns.

第一章 緒論 1
1.1 研究動機 1
1.2 內容大綱 1
第二章 相關研究 2
2.1 CMOS電路和PTL電路的比較 2
2.2 PTL電路合成器 4
2.3 PTL合成器之前段流程 6
第三章 以開關電晶體為主的佈局產生器 12
3.1 設計流程 12
3.2 佈局產生方法 15
3.2.1 PTL元件 15
3.2.2 產生佈局 17
3.2.3 改善連線長度 25
第四章 尋找最長路徑方法及其應用 33
4.1 尋找最長路徑之延遲時間 33
4.2 尋找test-pattern時可能的情況 38
4.3 產生test-pattern的方法 43
4.4 改善產生test-pattern的效率 45
4.5 其他應用 47
第五章 數據比較 48
5.1 產生test-pattern 48
5.2 佈局產生器和P&R tool(Soc encounter)的效能 50
第六章 未來展望 52
參考文獻 53

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