本論文以TSMC 0.18μm 1P6M CMOS製程，設計一個適用於802.11 WLAN 之Integer-N 1.8V頻率合成器。本文描述的頻率合成器包含相頻偵測器、電荷幫浦、迴路濾波器、以及pulse-swallow counter。在pulse-swallow counter方面，我們使用較少電晶體數目的前置除頻器工作於高頻區以降低功率消耗及減少晶片面積，以及提出一個改良的High-Speed CMOS programmable counter架構，此架構可工作於更高頻率和較低的功率消耗。我們完成2-GHz(共7個Channels)與5-GHz(共4個Channels)的pulse-swallow counter，此pulse-swallow counter的平均功率消耗分別為3.432 mW與2.98mW。使用Verilog-A撰寫而成的壓控振盪器(VCO)加入頻率合成器利用Spectre模擬整個頻率合成器證明了本頻率合成器的可行性。2-GHz 與5-GHz的頻率合成器的總功率消耗分別為3.432mW與4.673mW。

This thesis presents the CMOS integer-N frequency synthesizer for 2 GHz 802.11 WLAN applications with 1.8V power supply. The frequency synthesizer is fabricated in a TSMC 0.18μm CMOS 1P6M technology process. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a loop filter, and a pulse-swallow counter. In pulse-swallow counter, we use less numbers of transistors divide-by-2/3 prescaler to work in high frequency in order to reduce power consumption. We complete the design of pulse-swallow counter for 2-GHz (seven channels) and the 5-GHz (four channels) application. The average power consumption of pulse-swallow counter is 2.49 mW and 2.98 mW for 2-GHz and 5-GHz application respectively. We use Verilog-A language to complete VCO behavior model for frequency synthesizer and utilize the Spectre simulation results justify the feasibility of our proposed frequency synthesizer. The total power consumption of frequency synthesizer is 3.432mW and 4.673mW for 2-GHz and 5-GHz frequency synthesizer, respectively.

CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Thesis Organization 2
CHAPTER 2 THE CONCEPTS OF FREQUENCY SYNTHESIZER 3
2.1 Power Consumption Consideration 3
2.2 General Concepts 4
2.2.1 Sidebands 5
2.2.2 Lock Time 6
2.3 Types of Frequency Synthesizer 7
2.3.1 The Digital Synthesizer 7
2.3.2 The Direct Synthesizer 8
2.3.3 The Indirect Synthesizer 9
2.4 Frequency Synthesizer 10
2.4.1 Basic Concepts 10
2.4.2 Phase Frequency Detector (PFD) 11
2.4.3 Charge Pump and Loop Filter 16
2.4.4 Frequency Divider 18
CHAPTER 3 THE PROPOSED FREQUENCY SYNTHESIZER 21
3.1 Introduction 21
3.2 Frequency Divider 22
3.2.1 Divide-by-2/3 prescaler 24
3.2.2 Programmable Counter 26
3.2.3 Swallow Counter 31
3.2.4 Pulse-Swallow Counter 32
3.3 Phase-Frequency Detector (PFD) 33
3.4 Charge Pump (CP) 36
3.5 Loop Filter 39
3.6 VCO(with Verilog-A language) 41
CHAPTER 4 SIMULATION RESULT 44
4.1 RF Model 44
4.2 The Simulation of Divide-by-2/3 prescaler 44
4.3 The Simulation of Programmable Counter 46
4.4 The Simulation of Pulse-Swallow counter 49
4.4.1 Power Consumption of Pulse-Swallow Counter 52
4.5 The Simulation of PFD 54
4.6 The Simulation of PFD and Pulse-Swallow Counter 55
4.7 The Simulation of PFD, Charge Pump, and Loop Filter 57
4.8 The Simulation of Frequency Synthesizer 58
4.8.1 Open Loop Simulation 61
4.8.2 Lock Time 62
4.9 Layout 63
CHAPTER 5 CONCLUSION AND FUTURE WORK 68
5.1 Conclusion 68
5.2 Future Work 69
Reference 70

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