隨著晶片製程的進步，使得系統晶片的時代來臨，單一晶片內所包含的元件數越來越多，使得如何有效率的取得晶片內部訊號來幫助晶片設計者來進行驗證與除錯已成為一個重要的議題和挑戰。由於想觀察系統晶片內部的訊號與狀態相當困難，因此，對於晶片除錯面臨很困難的挑戰，在傳統的方法上是將欲觀察之訊號直接接到晶片腳位上，可以透過外部的邏輯分析儀，用以瞭解晶片內部運作的情形。然而由於晶片面積以及腳位的數目有限，即使使用此方式也無法獲得足夠的資訊，並且也會因為這種方式，使得晶片所需的腳位增加，進而增加晶片面積，使得成本也大幅上升。然而為了解決這個問題在我的研究中，最主要的目標是去建構一個可用於單晶片系統發展之多重解析匯流排資料追蹤的除錯環境，使用者可以依照自己的需求動態調整追蹤資訊的精準度，做法是內嵌一即時追蹤器於系統晶片中，此追蹤器可即時記錄欲觀察之系統訊號，並儲存於記憶體內(稱之為追蹤記憶體)，待系統停止後，將追蹤記憶體內容讀出至個人電腦，以分析軟體來解析系統狀況。然而由於晶片內部資料量十分龐大，因此此類追蹤器也伴隨著較佳的壓縮資料功能，用以增加追蹤深度。在分析軟體部份，我們將提供的不只是壓縮資料的解還原技術，並且將資料做進一步的分析，轉換成波形以及系統中狀態資訊，用以提供使用者做更進步的系統除錯。

Debugging in the System-on-a-Chip (SoC) environment is a challenge since it was hard to observe their signals on a chip. How to obtain the chip internal signals to help chip designers effective to verify and debug has become an important issue.It is impractical to observe their signals on output pins due to pin number limitation. The conventional solution is to embed a monitor within the hardware for capturing the signals in real time and storing them in a on-chip trace memory.
This thesis shows how the embedded multi-resolution AXI Bus Tracer can enable users to achieve the SoC debugging and performance evaluation efficiently, and it can trace the AXI Signals on the AMBA 3.0 AXI environment. Users can dynamically adjust the tracking resolution during the program execution, and we also provide an effective encoding algorithm for compressing the trace data. With our trace analysis software, we provide the detail information ranging from detail signal waveforms to transaction level waveforms, and transfer the trace signals into Value Change Dump (VCD) file. We also show several pie charts to analyze the portion of transfer types. In our work, we provide a synthesizable hardware to embed SOC for capturing signals. Then traced information through decompress and analysis can make users analyze system debugging and performance evaluation.

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Background 2
1.3 Research Methodology 4
Chapter 2 Related Work 5
2.1 Monitor Technology 5
2.1.1 BDU (Breakpoint Detection Unit) 5
2.1.2 Multipurpose/Multiprocessor Application Monitor 6
2.1.3 AHB Trace Buffer 7
2.1.4 Monitor-Based Test 8
2.1.5 Embedded Debug and Trace 10
2.2 Compression Techniques 13
2.2.1 Packed Differential Address and Time Stamp 13
2.2.2 Locality-Based Online Trace Compression 16
2.3 ARM Embedded Trace Macrocell (ETM) 17
2.4 First Silicon Solutions AMBA Navigator 18
2.5 AHB Bus Tracer 19
2.5.1 Multi-Resolution AMBA AHB Tracer 19
2.5.2 Trace Data Stored in On-Chip Memory 21
2.5.3 Modify for Multi-Resolution AMBA AXI Tracer 22
Chapter 3 Review Advanced eXtensible Interface 23
3.1 AMBA 3.0 Advanced eXtensible Interface 23
3.2 Comparison between the AXI and the AHB 25
Chapter 4 Multi-Resolution AXI Bus Tracer 26
4.1 AXI Bus Tracer in SoC Environment 27
4.2 Hardware Design of Multi-Resolution AXI Tracer 30
4.2.1 Abstraction Module 30
4.2.2 Compression Module 35
4.2.3 Packing Module and FIFO Module 39
4.2.4 Dynamic Mode Switch 42
4.2.5 Trace Data Stored in On-Chip Memory 45
4.3 Summary 46
Chapter 5 The Reverse-encoding Algorithm 47
5.1 Problem in Traditional Trace Compression 47
5.2 The Basic Reverse Compression Formulation 48
5.2.1 Differential Compression 50
5.2.2 Dictionary-based Compression 50
5.3 Circular Buffer Management 52
5.3 Summary 54
Chapter 6 Bus Analyzer 55
6.1 Decompression 55
6.1.1 Trace Data Reordering 56
6.1.2 Trace Data Unpacking 57
6.2 VCD Format Converting 59
6.2.1 Example of VCD File Format 59
6.2.2 Converting Trace Data to VCD File 61
6.3 Trace Data Analysis for Windows OS 62
6.3.1 Waveform Viewer 62
6.3.2 Address/Data Normal Distribution 63
6.3.3 Access Control Signals Analyzer 64
6.3.4 Protocol Control Signals Analyzer 65
6.3.5 Bus Transaction Model 66
6.4 Trace Data Analysis for Linux OS 67
6.5 Summary 68
Chapter 7 Verification 69
7.1 RTL Verification 70
7.1.1 Design Ware AMBA 3 AXI Verification IP 70
7.1.2 RTL Verification Environment 71
7.1.3 Automatic Verification 73
7.1.4 Coding Style Verification 74
7.1.5 Code/FSM Coverage Verification 74
7.2 FPGA Verification 76
Chapter 8 Debug Methodology 79
8.1 Pre-T/Post-T Trace 79
8.2 Power-On Trace 80
8.3 Cooperation with Event-based Debugger 84
8.4 Matching with Simulation Result 85
Chapter 9 Experimental Results 87
9.1 Compression Ratio 87
9.1.1 Environmental impact of the compression ratio 89
9.1.2 The Best and Worst Cases 93
9.1.3 Comprare with our AHB Bus Tracer 101
9.2 Analysis of the AXI and AHB Bus Utilizations 108
9.3 Case Study – JPEG Encoder Analysis 110
9.3.1 JPEG Encoder – SYS32TM Cache Disable 111
9.3.2 JPEG Encoder – SYS32TM Cache Enable 130
9.3.3 JPEG Encoder Program behavior Analysis 149
9.4 Comparison of AHB and AXI Transactions 152
9.4.1 Case 1: Two Master with Two Slave 153
9.4.2 Case 2: Two Master with One Slave 154
9.4.3 Case 1: One Master with One Slave 156
9.4.4 Summary 157
9.5 Analysis of Trace Depth on a Trace Memory 160
9.6 Hardware Synthesis 161
9.7 SoC Case Studies 162
9.7.1 An SoC with 3D Graphics Acceleration 163
9.7.2 Global unichip’s SoC Development Board 165
Chapter 10 Conclusion 170
Chapter 11 Future Work 172
References 173
Appendix A : I/O Definition 175
A.1 AXI Bus Tracer I/O Interface 175
A.2 AHB Bus TraceMemeory I/O Interface 176
Appendix B : Control Register 177
Trace Control Register Setup 182
Appendix C : Power-On Trace User Manual 184
Appendix D : Achievement 186

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