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博碩士論文 etd-0721113-174000 詳細資訊
Title page for etd-0721113-174000
論文名稱
Title
架構於去尾迴旋解碼器之預先錯誤修正器
Error Pre-Correction Architecture for Tail-biting Convolution Code Decoder
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
76
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2013-07-23
繳交日期
Date of Submission
2013-08-21
關鍵字
Keywords
去尾迴旋碼、維特比解碼器、無線通訊、低功率、預先錯誤修正器
pre-correction architecture, tail-biting convolutional code, low power, Viterbi decoder, wireless communication
統計
Statistics
本論文已被瀏覽 5658 次,被下載 290
The thesis/dissertation has been browsed 5658 times, has been downloaded 290 times.
中文摘要
因為無線通訊系統容易受到雜訊的侵襲進而造成訊號錯誤,所以傳送端通常會採用迴旋碼(Convolution code)將欲傳送的資料進行編碼,再藉由通道傳到接收端,而接收端則使用由維特比演算法(Viterbi Algorithm)所衍生而成的維特比解碼器(Viterbi decoder)進行解碼並且修正錯誤的位元。在現在3G行動通訊中,基地台與通訊元件之間經常使用此種解碼器作為主要的解碼機制。在行動通訊裝置上,由於傳統解碼器的功率消耗佔整個訊號接收器的三分之一甚至更高的比例,因此如何有效地減少無線通訊系統中維特比解碼器的功率消耗,將是本論文所探究的重點。
雖然維特比解碼器具有高效率的抗雜訊能力,但由於結構較複雜,所以功率消耗也比較大。為了降低功率消耗,我們可以在解碼資料要進入維特比解碼器前,預先偵測是否受到雜訊干擾並且判斷受到雜訊干擾的強度。假如雜訊干擾的情況不嚴重,就運用較簡單的預先錯誤修正器將收到的迴旋碼解回成原始資料,而不須再將資料送入到維特比解碼器裡進行解碼。
此外,傳統的迴旋編碼器在存活記憶體單元裡通常是使用歸零收尾方式(Zero -tail)來處理資料。這種編碼方式雖然有比較好的抗雜訊干擾能力,但卻會增加額外的收尾位元(Tail bit),這將促使碼率(Code rate)下降並且使得傳輸的效率變差,尤其在傳輸長度較短的資料時這種情況會特別明顯,例如封包的擋頭(Header)。而目前流行的去尾迴旋碼(Tail-biting convolution code)則可以改善此一缺點,與傳統的迴旋編碼做比較,它所具有的優勢就是能夠保持位元錯誤率不變的情況下,提高碼率(Code rate),因此近年來漸漸被用於長期演進(LTE)的控制通道。
本論文針對去尾迴旋碼設計一個簡單的預先錯誤修正器,用以減少解碼資料進入維特比解碼器的次數,進而減少維特比解碼器的功率消耗,使得整體電路的功率消耗下降。實驗數據顯示本論文提出的預先錯誤修正器能夠進一步改善錯誤偵測無法處理的資料,尤其在雜訊強度2dB至7dB的區段更是大幅度降低資料進入去尾迴旋解碼器的次數。因此,本論文所提出的方法確實可以讓去尾迴旋解碼器以及整體電路達到降低功率消耗的效果。
Abstract
The data will be interfered easily with noise in the channel. In the wireless communication system, convolutional encoder is commonly used in the sender now, and the receiver must use the corresponding deconvolution coder to correct and recover the data. In 3G mobile communication, Viterbi decoder often be used to correct and decode the encoded data by convolutional encoder. However, the traditional decoder consumes one-third of or even more power dissipation in the entire signal receiver. Therefore, this thesis focuses on how to effectively reduce the power consumption of Viterbi decoder in the wireless communication system.
Viterbi decoder has very good noise immunity but its the structure is complex, leading to high power consumption. The power consumption of Viterbi decoder can be reduced if it is skipped and replaced by a simple pre-corrector when the errors can be corrected with the simple pre-corrector.
Moreover, convolutional encoder usually uses zero-tail convolutional encoding method. This method has better noise immunity but will increase the extra tail bits, leading to bit rate decline and poor transmission efficiency. On the contrary, tail-biting convolutional encoding method is able to maintain constant bit rate, and is gradually popular for long-term evolution (LTE) control channel in recent years.
The objective of this thesis is to develop a simple pre-corrector for tail-biting convolution codes to decrease the amount of the received data fed in the tail-biting Viterbi decoder, so that the power consumption of the Viterbi decoder and the whole system can be reduced. The experimental results show that the proposed pre-correction architecture can significantly decrease the execution times of Viterbi decoder when the noise intensity is between 2dB to 7dB. Therefore, the proposed approach is indeed able to decrease the power consumption of tail-biting decoder and the whole system.
目次 Table of Contents
第一章 緒論 ……….1
1.1 研究背景 ……….1
1.2 研究動機與方式 ……….2
1.3 論文架構 ……….3
第二章 去尾迴旋系統之背景知識 ……….5
2.1 迴旋碼 ……….5
2.1.1 迴旋碼概述 ……….5
2.1.2 迴旋碼編碼架構 ……….6
2.2 維特比演算法概述 ……….10
2.2.1 維特比演算法簡介 ……….10
2.2.2 維特比解碼範例 ……….13
2.2.3 暫存器交換法 ……….16
2.2.4 追溯法 ……….17
2.3 去尾迴旋碼概述 ……….18
2.3.1 去尾迴旋碼簡介 ……….18
2.3.2 去尾迴旋碼演算法 ……….22
第三章 預先錯誤修正器 ……….25
3.1 迴旋碼之錯誤偵測簡介 ……….25
3.2 錯誤偵測與雜訊強度 ……….28
3.2.1 錯誤偵測之漏洞 ……….28
3.2.2 雜訊強度影響 ……….30
3.3 預先錯誤修正器與雜訊強度偵測器 ……….32
3.3.1 預先錯誤修正器 ……….32
3.3.2 雜訊強度偵測器 ……….34
第四章 硬體架構 ……….36
4.1 維特比解碼器硬體架構設計 ……….36
4.2 錯誤偵測及預先錯誤修正電路架構 ……….40
4.2.1 錯誤偵測器 ……….42
4.2.2 預先錯誤修正器 ……….45
4.2.3 錯誤強度偵測器 ……….47
第五章 驗證與實驗數據 ……….50
5.1 軟體模擬架構 ……….50
5.2 矽智產驗證 ……….51
5.3 硬體規格 ……….52
5.4 實驗數據 ……….53
第六章 結論與未來工作 ……….60
參考文獻 ……….61
參考文獻 References
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