因應製程的進步，科技的演變，嵌入式系統在現今電腦架構當中扮演著十分重要的角色，因其具有低成本與面積小的優勢提供可靠的效能執行特定的應用程式與任務。但受限於資源方面的限制，嵌入式系統需在效能與功耗之間取得完美的平衡以利系統可以長久的運作。快取記憶體為嵌入式系統當中負責快速提供中央處理器資料的記憶體，具有足夠的命中率與低延遲的優點，但卻也有著因應容量要求而使面積龐大與漏電的高功耗缺點。草稿記憶體(SPM：Scratchpad Memory)為一種進階使用快取記憶體之方法，具有高功耗效率與可預期性的存取延遲之優點，但是使用草稿記憶體需要占領一般快取記憶體一部分的容量並放置使用者選擇的資料，因此使用草稿記憶體將會使某一快取記憶體之set因未擁有足夠的空間放置資料而發生過度集中存取之狀況，導致命中率下降且效能降低。由於草稿記憶體使用之空間為data RAM，因此於此篇論文中，提出利用草稿記憶體之tag RAM做為過度存取之快取記憶體set的暫時性額外放置空間，實驗結果顯示最佳情況可降低衝突性失誤(conflict miss)至原本的0.85%，平均可降低至原本的28%。

Embedded system plays an important role in modern computer architecture since it can provide reliable performance with lower cost and area compared to the general computer. Due to its resource limitations, embedded systems need to take the balance between energy consumption and performance. Cache consumes most of the chip area to provide enough hit rate and lower latency than memory. However, the cache also takes a large amount of energy due to its chip area and leakage power. Scratchpad Memory (SPM) is commonly used in the embedded system and has the advantages of energy-efficiency and predictable timing, but using SPM requires normal cache ways to hold the specific data during program execution. Each program has its unique cache requirement from execution start to end which leads to different proportion of normal cache ways and SPM ways. Hot cache sets are caused when some cache sets have fewer cache blocks to place data which leads to higher conflict miss rate. In this paper, we propose an adaptive tag-based spare cache architecture to solve hot cache sets problem during each program execution. The experiment results show 99.15% conflict miss reduction in the best case and 75.33% in average of MiBench.

論文審定書 i
摘要 iii
Abstract iv
Contents v
List of Figures vii
List of Tables ix
Listing of Listing x
Chapter 1. Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 Organization of the Thesis 3
Chapter 2. Related Works 5
2.1 Hybrid SPM-Cache Architecture 6
2.2 Cache Sets Utilization 7
2.3 Cache Miss Reduction 8
2.4 Additional Functions 10
2.5 Problem Discussions 12
Chapter 3. Hot Cache Sets Analysis 13
3.1 Program Execution Address 13
3.2 GEM5 14
3.3 Dinero IV 15
3.3.1 Normal Cache Operation 15
3.3.2 SPM Data Address and Removement 16
3.3.3 Spare Cache Data Block 17
Chapter 4. Spare Cache Architecture 19
4.1 Architecture Overview 20
4.2 Tag RAM Input Classifier 22
4.2.1 Spare Cache Access Table 24
4.2.2 Tag Signals Selection 27
Chapter 5. Experimental Results 30
5.1 Conflict Miss Reduction 31
5.1.1 Experiment Setup 31
5.1.2 Reduced Conflict Miss Results 32
5.1.3 Data Interference 34
5.2 Timing Analysis - Critical Path 37
5.3 Hardware Implementation - Gate Counts 38
5.4 Power Consumption Analysis 39
Chapter 6. Conclusion 41
Chapter 7. Future Work 42
References 43
Appendix A Cache Miss Calculation 46

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