在這篇論文中，我們介紹一個較新的低功率乘法器設計，不同於以往常被用來設計乘法器的進位保留陣列 (carry save array)，我們改以漣波進位陣列 (ripple carry array)為基礎，再利用旁通電路(bypassing logic)來設計我們的乘法器，藉此來減少轉態次數(switching activities)進而達到低功率的需求，並且利用簡單的樹狀結構來提升我們乘法器的效能。使用漣波進位陣列乘法器來設計旁通型乘法器的好處是它可以使用較少的額外的判斷邏輯就可達到旁通的目地，而且和傳統陣列乘法器相較之下，也可以節省更多的功率。整個電路我們以TSMC 0.18um製程來製作並使用Hspice工具來進行模擬測試。根據模擬結果顯示，我們提出的乘法器相對於傳統陣列乘法器可以節省約15%的功率消秏，雖然必須付出一些面積上的代價。

In this thesis, a novel low power multiplier design is introduced. We utilize the bypassing logic to construct a multiplier based on ripple carry array to minimize the switching activities rather than carry save array for the low power requirement and tree structure to enhance the performance. The advantage of using the bypassing logic in the ripple carry array multiplier is that it can use less extra hardware and achieve more power saving compared with conventional multipliers. The design of our circuit uses the standard TSMC 0.18um technology and simulates with Hspice. According to the simulation results, the proposed design can obtain power saving around 15% more than conventional multipliers, although it must occupy larger area.

CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Contribution 1
1.3 Thesis Organization 2
CHAPTER 2 PRIMINARIES 3
2.1 Power Dissipation 3
2.2 Concept of Multipliers 6
2.2.1 Conventional Multipliers 7
2.2.1.1 Iterative Multipliers 7
2.2.1.2 Array Multipliers 8
2.2.2 Baugh-Wooley Multiplication [3] 10
2.3 Related Works 13
CHAPTER 3 CIRCUIT DESIGN 16
3.1 Concept of Bypassing Method 17
3.2 Bypassing Multiplier [11] 18
3.3 A Ripple-Carry Array Multiplier with Row Bypassing 20
3.4 Comparison of [11] and Proposed Multiplier 24
3.5 A Ripple-Carry Array Multiplier with Row Bypassing and Tree Structure 25
3.6 Signed Multiplier 28
3.6.1 Signed Bypassing Multiplier 29
3.6.2 A Signed Ripple-Carry Array Multiplier with Row Bypassing and Tree Structure 30
CHAPTER 4 SIMULATION RESULTS 34
4.1 Unsigned Multipliers 35
4.2 Signed Multipliers 37
CHAPTER 5 CONCLUSION 40
5.1 Conclusion 40
5.2 Future Work 40
Bibliography 41

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