本論文主要可分為三個部份。第一部份(第二章)說明功率放大器的分類、特性以及其設計原理，由於A類功率放大器擁有較高的輸出功率以及線性度，因此採用A類功率放大器的架構來設計。第二部份(第三章)為設計以及模擬與量測結果比較操作於5.8 GHz之CMOS 0.18 um 二級串疊組態A類功率放大器，兩個功率放大器分別有18 dBm以及17.6 dBm的功率增益，23 %以及20.5 %的功率附加效率，19 dB以及22.5 dB的功率增益和15.2 dBm以及14.5 dBm的1dB壓縮點，面積分別為0.79 mm2以及0.77 mm2。第三部份(第四章)探討利用IPD(integrated passive device)製程電感取代CMOS製程電感並和CMOS製程共設計之功率放大器之模擬結果。由於IPD製程擁有低基板損耗以及高品質因子，可減少被動元件產生的損耗。但是在IPD下針焊墊(pad)以及CMOS晶片間的走線所產生的寄生電感效應會影響功率放大器的特性，本章詳細地討論共設計之寄生效應問題。第五章是結論與未來工作。

This thesis includes three major parts. The first part (chapter II) describes power amplifier classification, characteristics and design principles. Because class A power amplifier has higher output power and linearity, this configuration has been used to design power amplifier. In the second part (chapter III), two CMOS 0.18 um two stages class A cascode configured power amplifiers were designed at 5.8 GHz. They respectively exhibited saturated output power of 18-dBm and 17.6-dBm, PAE of 23-% and 20.5-%, power gain of 19-dB and 22.5-dB, P1dB of 15.2-dBm and 14.5-dBm, and with chip areas of 0.79 mm2 and 0.77 mm2. The third part (chapter IV) explores simulation results of the CMOS power amplifiers integrated with IPD (integrated passive device) inductors, instead of the on-chip CMOS inductors. Because IPD process has low substrate loss and high quality factor, the loss of passive device can be decreased. But, the path parasitic inductance between IPD pad and CMOS chip could degrades the power amplifier characteristics. This chapter discusses the parasitic effect of co-design in detail. Chapter V is the conclusions and future work.

論文審定書 i
誌謝 ii
摘要 iv
Abstract v
目錄 vi
圖表目錄 viii
第一章 緒論 1
1.1 背景簡介 1
1.2 研究動機 2
1.3 論文架構 3
第二章 功率放大器設計原理與特性 4
2.1簡介 4
2.2放大器的分類 4
2.3放大器的非線性特性 8
2.4穩定度 13
2.5負載線與負載拉移法 15
2.6功率增益和匹配網路設計 21
2.7功率附加效率 22
第三章 A類串疊組態功率放大器 23
3.1串疊組態 24
3.2兩級式A類串疊組態功率放大器之一 25
3.3兩級式A類串疊組態功率放大器之二 32
3.4結語 39
第四章 IPD電感與CMOS共設計之功率放大器 41
4.1 IPD製程 42
4.2晶片與晶片之間連接方式的比較 43
4.3 IPD電感與CMOS共設計之功率放大器 43
4.4結語 55
第五章 結論與未來工作 57
參考文獻 62

[1] D. M. Pozar, Microwave and RF Design of Wireless Systems, Norwood, MA:John Wiley & Sons, Inc., 2001.
[2] T. H. Lee, ”CMOS RF Integrated Circuits: Past, Present and Future,” Microwave Conference, vol.1, pp.12-19, October 1999.
[3] Iulian Rosu, RF Power Amplifiers, http://www.qsl.net/va3iyl.
[4] D. M. Pozar, Microwave Engineering, 3rd ed., MA:John Wiley & Sons, Inc, 2005.
[5] P. B. Kenington, High-Linearity RF amplifier Design, Norwood, MA:Artech House, 2000.
[6] S. C. Cripps, RF Power Amplifiers for Wireless Communications, Norwood, MA:Artech House, 1999.
[7] S. C. Cripps, Advanced Techniques in RF Power Amplifier Design, Norwood, MA:Artech House, 2002.
[8] Power Amplifier Design and Simulation Using ADS, Lecture of National Chip Implementation Center.
[9] B. Razavi, Design of Analog CMOS Integrated Circuits, NewYork, McGraw-Hill, Inc., 2000.
[10] C. C. Wang, H. A. Yang, Y. C. Shyu, M. H. Li, C. T. Chiu, S. M. Wu, C. W. Kuo and C. P. Hung, “Analysis of high performance RF integrated passive circuits using the glass substrate,”Proc. IEEE 9th VLSI Packag. Workshop Jpn., pp.135 -138, 2008.
[11] H. K. Chen, Y. C. Hsu, T. Y. Lin, D. C. Chang, Y. Z. Juang and S. S. Lu, “CMOS wideband LNA design using integrated passive device,” in Proc. IEEE MTT-S Int. Microw. Symp. Dig., Boston, MA, Jun. 2009, pp.673–676.
[12] Y. C. Hsu, H. K. Chieo, H. K. Chen, T. Y. Lin and D. C. Chang, “Low phase noise and low power consumption VCOs using CMOS and IPD technologies,” IEEE Trans. Components, Packaging and Manufacturing Tech. ,vol. 1 ,pp. 673-680 ,MAY 2011.
[13] 探微科技股份有限公司, http://www.tmt-mems.com/
[14] M. Engl, K. Pressel, H. Theuss, J. Dangelmaier, W. Eurskens, H. Knapp, W. Simbuerger and R. Weigel, “Evaluation of Wirebond and Flip-Chip Interconnects of a Leadless Plastic Package for RF Applications, Proc. Electron. Packag. Technol. Conf., pp.304-308, 2005.
[15] T. Krems W. Haydi, H. Massler, and J. Rudiger, “Millimeter-Wave Performance of Chip Interconnections Using Wire Bonding and Flip Chip,” IEEE MTT-S Int. Microwave Symposium Digest, pp.247-250, Jun. 1996.
[16] J. H. Lau and R. Chen, “Cost Analysis: Solder bumped Flip Chip versus Wire Bonding,” IEEE Proceedings of Int'l Electronics Manufacturing Technology Symposium, pp464- 472, Oct. 1998
[17] J. H. Lau, “TSV Manufacturing Yield and Hidden Costs for 3D IC Integration,” Proceedings of Electronic Components and Technology Conference 2010, Jul. 2010, Las Vegas, USA, pp. 1031-1042.
[18] G. C. Lin and Z. M. Lin, “A 5.8-GHz fully-integrated power amplifier for 802.11a WLAN system,” in Proc. IEEE Conference on Electron Devices and Solid-State Circuits,pp.1013-1016, Dec. 2007.
[19] C. Lu, A. V. H. Pham, M. Shaw and C. Saint, “Linearization of CMOS Broadband Power Amplifiers Through Combined Multigated Transistors and Capacitance Compensation,” IEEE Trans. Microw. Theory Tech.,vol. 55, no. 11, pp.2320–2328, Nov. 2007.
[20] F. Y. Xing, L. Sun and Y. J. Peng, “A CMOS power amplifier for 5.8GHz DSRC application,” Microwave and Millimeter Wave Technology (ICMMT), vol. 5, pp.1-4, May 2012.
[21] N. Demire, Y. Pinto, C. Calvez, D. Titz, C. Luxey, C. Person, D. Gloria, D. Belot, D. Pache, and E. Kerherve, “Codesign of a PA-Antenna Block in Silicon Technology for 80-GHz Radar Application,” IEEE Trans. Circuits Syst. II, vol. 60, pp. 177-181, Apr. 2013.