近年來,使用分離獨立缺陷的記憶胞當作電荷儲存中心已經被廣泛的研究,期望成為取代傳統DRAM或快閃記憶體的候選產品,傳統的浮停閘非揮發性記憶體在元件尺寸小於五十奈米即遇到設計上的瓶頸。傳統浮停閘記憶体為了達到非揮發性的特性需要,控制和較厚的穿隧氧化層才可以有更長的資料儲存持久性,奈米點記憶體中,電荷對氧化層局部缺陷的流失較不受影響,所以提昇了元件的資料儲存持久性,所以奈米點記憶體可以比快閃記憶體元件容許更彈性的穿隧氧化層設計,藉以提供更好的操作電壓,寫入抹除速度,資料儲存持久性,資料操作容忍性。
金屬奈米點勝過於其他相關材料的優點,包含更高的能態密度,對通道層有更高的耦合,更佳的尺寸設計控制和更自由的功函數搭配選擇來達到最佳的電性.然而,鎢奈米點在所有金屬奈米點中最讓人感興趣,鎢有許多吸引人的優點,例如極高的熔點,很高的製程溫度使元件有優越的熱穩定性,現今超大型積體電路技術應用廣泛,使鎢奈米點非揮發性記憶體在工業上的實際可能生產。
本篇論文在敘述鎢奈米點記憶體電容元件的製作過程,形成機制以及電性分析。我們使用兩種不同氣體(O2/N2O)的快速熱氧化回火長出的穿隧氧化層,再用低壓化學氣相沉積(LPCVD)成長矽化鎢/非晶矽雙層疊層薄膜,最後以高溫快速熱氧化回火方式在穿隧氧化層上方氧化形成鎢奈米點以及控制氧化層。由電性量測可知,鎢奈米點記憶體電容的電容-電壓曲線記憶窗必須在製程900°C/60秒以上並且在矽化鎢上沉積非晶矽一並回火才會被觀察到,而在製程溫度更高時間更長,達到1050°C/120秒才會有較好的電子(洞)儲存特性。由電性分析得知,利用N2O氣體回火至成的穿隧氧化層雖然在電荷儲存特性不如純O2氣體的製程,但是卓越的耐操度電性讓人值得進一步研究,因為耐操度(Endurance)對非揮發性記憶體的應用上是很重要的電性 。另外,我們有製作出基本奈米點元件延伸的新結構元件,包括N2O氧化製程,還有氨電漿處理形成新儲存層的研究,形成一種奈米點與SONOS結構合併的新結構記憶體。最後,我們將超臨界二氧化碳(Supercritical CO2 , SCCO2)應用在鎢奈米點記憶體中,我們發現超臨界二氧化碳不但可以增進鎢奈米點記憶體的電性,並且可以製造出類似於高溫製程的鎢奈米點記憶體,我們推估超臨界二氧化碳搭配水氣類似一種低溫氧化製程,此種新穎的氧化製程在半導體製造業具有相當吸引人的特性與優點。

Recently, memory-cells employing discrete traps as the charge storage media have been attracting a lot of attention as a promising candidate to replace conventional DRAM or Flash memories. Conventional floating gate (FG) non-volatile memories (NVMs) present critical issues on device scalability beyond the sub-50nm node. In achieving non-volatility in conventional FG memories, thicker control and tunnel oxide (~8nm) are required to guarantee longer retention time. Relatively, nano-dots memories causes more resistant leakage charges by localized storage sites, thus improving the device retention characteristics. Hence, nano-dots memories allow more aggressive scaling of the tunnel oxide and exhibit superior characteristics compared to Flash memories in term of operation voltage, write / erase speed, retention time and endurance.
The advantages of metal nano-dots compared with other material counterparts include higher density of states , stronger coupling with the channel, better size scalability, and the design freedom of engineering the work function to optimize device characteristics. However, tungsten nano-dots are the most interested in all of metal dots is that tungsten metal has more extra attractive advantages, such as ultra high melting point make high process temperature caused superior thermal stability of device and wide application in VLSI technology nowadays caused real possibility of tungsten nano-dots NVMs fabricated in industry in practice.
This dissertation is divided into four sections: (1) discussion of basic properties for tungsten nano-dots memory devices; (2) Tunneling Oxide Engineering,; (3) Improvement by novel processes; and (4) The influence with supercritical CO2 (SCCO2) and vapor treatment. Initially, formative mechanism of tungsten nano-dots and electrical characteristics of devices was investigated in the first section. Tungsten nano-dots were formed by oxidizing tungsten silicide / amorphous silicon double stack film at high temperature condition. From electrical measurement, the better characteristics have been achieved for oxidation condition at 1050°C / 120 sec. Secondly, the rapid thermal anneal (RTA) oxidation is used to grow tunnel oxide by two different forming gas (O2/N2O). Comparison of electrical characteristics, program characteristics of the device using tunnel oxide with N2O process is inferior than the common device. However, endurance is a important electrical characteristics in the semiconductor device especially apply on the non-volatile memory. Thirdly, novel processes were employed into fabrication of tungsten nano-dots memory devices, include the N2O oxidation and NH3 plasma treatment. The purpose of novel processes is production additional trapping states in nonvolatile memories, which is considerably as combination nano-dots with SONOS structure. In the final section, the application of supercritical CO2 with vapor on tungsten nano-dots memoery devices have been studying. It is found that the device treated by SCCO2 which electrical characteristics is improved obviously. Furthermore, this technology also can fabricate the nano-dots memory which is like the device used high temperature oxidation process. It suggests that the SCCO2 with vapor treatment could oxidize silicide film under a low temperature environment. This novel oxidation process has some advantages and could be noticed in the semiconductor industry.

Contents

Chinese Abstract………………………………………………………………..i
English Abstract…………………………………………………………iii
Acknowledgement………………………………………………………..v
Contents…………………………………………………………………..vi
Table Captions …………………………………………………………..ix
Figure Captions………………………………………………………..…x

Chapter 1 Introduction
1.1 Non-Volatile Memories ………………………………………………….......1
1.2 Nano-dots Non-Volatile Memories (NVMs)…………………………………5
1.3 Motivation…………………………………………………………….………9
1.4 Organization of the Dissertation………………………………………….…10
Figures………………………………………………………………………12

Chapter 2 Tungsten nano-dots NVMs
2.1 Introduction……………………………….…………………………………15
2.2 Process Flow and Basic Electrical Characteristics of Tungsten Nano-dots NVMs……………………………………………………………………….16
2.3 Mechanism of Tungsten Silicide Oxidation……….………………..………19
2.4 Formation Model of W-dots NVMs Used RTP and Study of Energy Band Diagram……………………………………………………………………..23
2.5 Study of Reliability of Tungsten Nano-dots NVMs…………………...……28
2.6 Discussion of W-dots NVMs used WSi2 with High Si/W Ratio Process…....32
2.7 Summary……………….……………………………………………………34
Figures……………………………………………………………………….36

Chapter 3 Study on of Tunneling Oxide Engineering with Tungsten Nano-dots NVMs
3.1 Introduction………………………………………………….………………51
3.2 Mechanism and Process Discussion of Tungsten Nano-dots NVMs Used Tunneling Oxide with N2O Process...……………………………………….52
3.2.1 Mechanism Discussion of Tunneling Oxide used N2O process………52
3.2.2 Process Analysis of Tungsten Nano-dots NVMs Used Tunneling Oxide with N2O Process……………………………………………….……54
3.3 Electrical Analysis of Tungsten Nano-dots NVMs Used Tunneling Oxide with N2O Process……………………………………………………………56
3.3.1 Basics Electrical Characteristics Analysis of W-dots NVMs Used TO-N2O………………………………………………………………56
3.3.2 Endurance Electrical Characteristics Analysis of W-dots NVMs Used
TO-N2O………………………………………………………………59
3.4 Electrical Characteristics Analysis of Tungsten Nano-dots NVMs Used thick Tunnel Oxide……….…………………………………….…………………61
3.5 Summary……………………………………………....……………………63
Figures………………………………………………………………………65

Chapter 4 Novel Process Application on Tungsten Nano-dots NVMs
4.1 Introduction …………………………………………………………………76
4.2 Fabrication of Novel Tungsten Nano-dots NVMs used N2O Oxidation Process………………………………………………………………....……76
4.2.1 Process Discussion of Tungsten Nano-dots NVMs Used N2O Oxidation
Process………………………..……………………………….………76
4.2.2 Electrical Characteristics of Tungsten Nano-dots NVMs Used N2O Oxidation Process………………………………………………….…78
4.3 Implement of Trapping Layer Employed in Tungsten Nano-dots NVMs by NH3 Plasma Process………………………………………………..………81
4.4 Summary………………………………………………….…………………84
Figures………………………………………………………………………85

Chapter 5 Application of Supercritical CO2 on Tungsten Nano-dots NVMs
5.1 Introduction…………………………………….……………………………93
5.2 The Mechanisms of SCCO2 Process…………………...……………………94
5.3 The Improvement of Electrical Characteristics on Tungsten Nano-dots NVMs by SCCO2 Treatment………………………………..………………………96
5.4 Fabrication of Tungsten Nano-dots with SCCO2 Treatment………………..99
5.5 Summary…………………………………………………………………...101
Figures……………………………………………………………………..103

Chapter 6 Conclusions and Suggestions for the Future work
6.1 Conclusions………………………………………………………………...110
6.2 Suggestions for Future Work ……………………………………………...112

Reference……………………………………………………….………………...114

Reference
Chapter 1:
[1.1] D.Kahng and S.M.Sze, ”A Floating Gate and Its Application to Memory Device,” Bell Syst.
Tech., 46,1283(1967)
[1.2] “Advanced Memory Technology and Architecture”, short course, IEDM 2001
[1.3] T. Ohnakado, H. Onada, O. Sakamato, K. Hayashi, N. Nishioka, H. Takada, K. Sugahara, N.
Ajika and S. Satoh, “Device characterisitics of 0.35μm P-channel DINOR flash memory
using band-to-band tunneling-induced hot electron (BBHE) programming”, IEEE Trans.
Electron Device, Vol 46, pp 1866-1871, 1999.
[1.4] T.P.Ma, “Marking silicon nitride film a viable gate dielectric”, IEEE Trans. Electron Device,
45(3), pp 680-690, 1998.
[1.5] Flash Memories , edited by P. Cappelletti et al., Kluwer Acadenic Publishers, 1999
[1.6] R-L. Lin, Y.-S. Wang and Chairs C-H Hsu, “Muti-level P-channel flash memory”, The 5th
International Conference on Solid-State and Integrated Circuit Technology, pp. 457, 1998.
[1.7] D. Forhman-Bentchkowsky, “Memory behavior in a floating-gate avalanche-injection
MOS(FAMOS) structure”, Appl. Phy. Lett., vol. 18,pp 332-334, 1971.
[1.8] --,“FAMOS-A new Semiconductor charge storage device”, Solid State Electron., vol. 17,pp.
517-520, 1974.
[1.9] V. N. Kynett, A. Baker, M. Fandrich, G. Hoekstra, O. Jungroth, J Kreifels, and S. Wells, “An
in-system reprogrammable 256K CMOS Flash memory2,” in ISSCC Conf. Proc., 1988,
pp.132-133.
[1.10] F. Masuoka, M. Momodomi, Y. Iwata, and R. Shirota, “New ultra high density EPROM
and Flash with NAND structure cell,” in IEDM Tech. Dig., 1987, pp.552-555.
[1.11] S. Aritome, “Advance Flash memory technology and trends for file storage application,” in
IEDM Tech Dig., 2000, pp. 763-766.
[1.12] S. Lai, “Flash memories: Where we were and where we are going,” in IEDM Tech. Dig.,
1998, pp. 971-973.
[1.13] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cell—An overview,” Proc. IEEE,
vol. 85, pp 1248-1271, Aug. 1997.
[1.14] P. Pavan and R. Bez, “The industry standard Flash memory cell in Flash memories,” P.
Cappelletti et al., Ed. Norwell, MA: Kluwer, 1999.
[1.15] P. Cappelletti, C. Golla, P. Olivo, E. Zanoni, “Flash Memories”, Kluwer Academic,
Norwell, 2000.
[1.16] KUWANO Masajiko, ”Memory IC,” CQ, Tokyo, 2001.
[1.17] TOSHIBA America Electronics Components, “NAND vs NOR Flash Memory Technology
Overview.”
[1.18] A. Thean and J. P. Leburton, “Flash memory: towards single-electronics,” IEEE, Oct 2002.
[1.19] International Technology Roadmap For Semiconductors 2006 Update.
[1.20] Y. S. Shin, “Non-volatile Memory Technologies for Beyond 2010”, Symposium on VLSI Circuits Digest of Technical Papers, 2005, pp.156-159.
[1.21] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and Doug Buchanan, “Volatile adn non-volatile memories in silicon with nano-crystal storage,” IEDM Tech. Dig., pp.521-524 Dec. 1995.
[1.22] Y. Yang, A. Purwar, and M. H. White, “Reliability considerations in scaled SONOS nonvolatile memory device,” Solid-State Electronics, vol.43, pp.2025-2032, May 1999.
[1.23] Z. Liu, C. Lee, V, Narayanan, G. Pei, and E.C Kan, IEEE Tran. Electron Device 49, 1606,
2002.
[1.24] Y. C. King, T. J. King, and C. Hu, IEEE Trans. Electron Device, 48, 2001, pp696.
[1.25] F. K. LeGoues, Rosenberg, T. Nguyen, F. Himpsel, and B.S. Meyerson, J. Appl. Phys., 65, 1724, 1989.
[1.26] J. Eugene, F. K. LeGoues, V.P.Kesan, S.S. Iyer, and F. M. d’Heurle, Appl. Phys. Lett., 59 78, 1991.
[1.27] J. J. Lee, X. Wang, W. Bai, N. Lu, and D. L. Kwong, IEEE Trans. Electron Devices, ”Theoretical and experimental investigation of Si nanocrystal memory device with HfO2 high-k tunneling dielectric,” 50, 2067, 2003.
[1.28] I. Kim, S. Han, H. Kim, J. Lee, B. Choi, S. Hwang, D. Ahn, and H. Shin, IEEE Int. Electron Device Meeting Tech. Dig., 1998, pp.111-114.
[1.29] A. Fernandes, B. DeSalvo, T. Baron, J. F. Damlencourt, A. M. Papon, D. Lafound, D. Mariolle, B. Guillaumot, P. Besson, G. Ghibaudo, G. Pananakakis, F. Martin, and S. Haukka, IEEE Int. Electron Device Meeting Tech. Dig., 2001, pp. 155-158.
[1.30] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories-partⅡ: electrical characteristics,” IEEE Trans. Electron Device, 49, 1614, 2002.
[1.31] S. Baik and K.S.Lim, Appl. Phys. Lett., 81, 5186, 2002.
[1.32] S.P. Murarka, “Silicides for VLSI applications”, Academic Press, INC., London, 1983, pp3-4
[1.33] S.K.Samanta, P.K. Singh, Won Jong Yoo, Ganesh Samudra, Yee-Chia Yeo, L. K. Bera, and N. Balasubramanian, ”Enhancement of Memory Window in short Channel Non-Volatile Memory Device Using Double Layer Tungsten Nanocrystal”, IEEE, 2005

Chapter 2 :

[2.1] James D. Plummer, Micharl D. Deal, Peter B. Griffin,” Silicon VLSI Technology: Fundamental, Practice and Modeling”, Prentice Hall, 2003.
[2.2] www.lasurface.com/database, ref.111.
[2.3] www.lasurface.com/database, ref 13, 111, 150.
[2.4] M. KATOH and T. TAKBDA, ”Chemical State Analysis of Tungsten and Tungsten Oxides Using an Electron Probe Microanalyzer,” J. J. Appl. Phy, Vol 43, No 10, 2004, pp. 7297-7295
[2.5] H. QIU and Y. F. LU, “Scanning Tunneling Microscopy and Atomic Force Microscopy Studies of Laser Irradiation of Amorpgous WO3 Thin Films”, J.J. Appl. Phys, Vol. 39, 2000, pp.5889-5893.
[2.6] S.P. Murarka, “Silicides for VLSI applications”, Academic Press, INC., London, 1983.
[2.7] Robert Beyers, “Thermodynamic considerations in refractory metal-silicon-oxygen systems”, J. Appl. Phys., 56(1), 1 July 1984, pp147-152.
[2.8] S. Zirinsky, W. Hammer, F d’Herurle, and J. Baglin, “Oxidation mechanism in WSi2 thin films”, Appl. Phys. Lett. 33(1), 1 July 1978, pp76-78.
[2.9] S. M. Sze, Kwok k. NG, “Physic of Semiconductor Device”, Wiley, New Jersey, 2007,
pp350-356.

Chapter 3:

[3.1] E. C. Carr and R.A. Buhrman, “Role of interfacial nitrogen in improving thin silicon oxide grown in N2O,” Appl. Phys. pp.54-56
[3.2] U. sharma, R. Moazzami, P. Tobin, Y. Okada, S. K. Cheng and J. Yeargain, “Vertical Scaled High Reliability EEPROM Device with Ultra-thin Oxynitride Film Prepared by RTP in N2O/O2 Ambient,” IEEE IEDM, Tech. Dig., 1992, pp 461-464
[3.3] P. J. Tobin, Yoshio Okada, Sergio A. Ajuria, Vikas Lakhotia, W. A. Feil, and R. I. Hedge. “Furnace formation of silicon oxynitride thin dielectrics in nitrous oxide (N2O): The role of nitric oxide (NO)”, J. Appl. Phys 75(3), 1994 Feb, pp1881-1817.
[3.4] C. Tsamis, D.N. Kouvatsos, and D. Tsoukalas, “Influence of N2O oxidation of silicon on point defect injection kinetics in the high temperature regime”, Appl. Phys. Lett., 69(18), 28 October 1996, pp2725-2727
[3.5] J. Kim, J. D. Choi, W. C. Shin, D. J. Kim, H. S. Kim, K. Mang, S. T. Ahn and O. H. Kwon, ”Scaling Down of Tunnel Oxynitride in NANS Flash Memory: Oxynitride Selection and Raliability”, IEEE, 1997
[3.6] M. Kato, N. Miyamoto, H. Kume, A. Satoh, T. Adachi, M. Ushiyama and K. Kimura, “Read-Disturb Degradation Mechanism due to Electron Trapping in the Tunnel Oxide for Low-Voltage Flash Memories,” IEEE IEDM, Tech, Dig., 1994, pp. 45-48.
[3.7] J. De Blauwe, J. Van Houdt, D. Wellekens, R. Degraeve, Ph. Roussel, L. Haspeslagh, L. Deferm, G. Groeseneken and H. E. Maes, “A New quantitative model to predict SILC-related disturb characteristics in Flash EEPROM devices,” IEEE IEDM, Tech. Dig., 1996, pp343-346.

Chapter 4:
[4.1] E. C. Carr and R.A. Buhrman, “Role of interfacial nitrogen in improving thin silicon oxide grown in N2O,” App. Phys. pp.54-56
[4.2] P. J. Tobin, Yoshio Okada, Sergio A. Ajuria, Vikas Lakhotia, W. A. Feil, and R. I. Hedge. “Furnace formation of silicon oxynitride thin dielectrics in nitrous oxide (N2O): The role of nitric oxide (NO)”, J. Appl. Phys 75(3), 1994 Feb, pp1881-1817.

Chapter 5:

[5.1] P. T. Liu, C. T. Tsai, T. C. Chang, K. T. Kin, P. L. Chang, IEEE Trans. Nanotech., 6(1), 29 (2007).
[5.2] P.T. Liu, C.T Tsai, P.Y. Yang, “Effects of supercritical CO2 fluid on sputter-deposited hafnium oxide”, Appl 90, 223101, 2007
[5.3] T. Sameshima, K. Sakamoto, Y. Tsunoda, and T. Saitoh, Jap. J. Appl. Phys., 37(2, 12A), L1452 (1998).
[5.4] M. Kunii, Jap. J. Appl. Phys., 45(2A), 660 (2006).