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博碩士論文 etd-0723109-003834 詳細資訊
Title page for etd-0723109-003834
論文名稱
Title
具有源極/汲極縛點新式假三閘極垂直式極薄金氧半場效電晶體之短通道效應與熱行為探討
Investigate Short-Channel Effects and Thermal Behavior of a Novel Pseudo Tri-Gate Vertical Ultrathin MOSFETs with Source/Drain Tie
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
113
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2009-06-26
繳交日期
Date of Submission
2009-07-23
關鍵字
Keywords
短通道效應、垂直式金氧半場效應電晶體、熱穩定、自我加熱效應
thermal stability, short channel effect, vertical MOSFET, self-heating effect
統計
Statistics
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The thesis/dissertation has been browsed 5981 times, has been downloaded 7766 times.
中文摘要
本論文研究具有源極/汲極縛點之新式假閘極垂直式極薄通道金氧半場效應電晶體(PTG-SDT VMOS)的元件行為,這源極/汲極縛點能抑止短通道效應的發生,而雙環繞式閘極(包含中間閘極與邊襯式閘極)被提出來研究與源極/汲極縛點的影響,根據二維模擬結果,我們提出三種假閘極垂直式場效電晶體:1.具有源極/汲極縛點之新式假閘極垂直式場效電晶體的元件特性:可以緩和自我加熱效應,此外能增加汲極驅動電流與熱穩定性。也由於它的極薄通道(通道厚度十奈米),具有源極/汲極縛點之假閘極垂直式金氧半場效電晶體在通道90 nm微縮至40 nm時,具有非常低的次臨限擺幅(SS = 60 mV/dec),也被發現有效的控制汲極引致能障下降DIBL以及在通道長度40nm時具有良好的輸出傳導(4.5 mS/μm)。2.我們提出一具有自然形成源極�汲極縛點(the natural source/drain tie, SDT)、較大源極�汲極縛點( the big source/drain tie, BSDT)、源極�汲極縛點(source/drain tie, SDT)與不具有源極�汲極縛點(without source/drain tie, WSDT)之極薄通道假閘極垂直式金氧半場效電晶體,在PTG VMOS這新結構能抑制短通道效應,而自然形成源極�汲極縛點被提出來與PTG VMOS做研究,根據二維模擬結果,PTG-NSDT亦展現出良好的熱驅散,就如汲極電極在垂直通道上端與下端時的晶格溫度特別地被改善47%與66%,此外增強了ON狀態與OFF狀態電流比。而閘極引致汲極漏電流(Gate-induced barrier lowing, GIDL)當源極與汲極電極接點位置互換時,在本體偏壓與溫度特性上的發展而被討論。雖然PTG VMOS維持雙環繞式閘極與源極/汲極縛點的結構,其設計製作流程更精簡甚至增加了汲極驅動電流並且能舒緩自我加熱效應的問題。
Abstract
This paper investigates the device behavior of a novel pseudo tri-gate ultrathin channel vertical MOSFET with source/drain tie (S/D tie), the PTG-SDT VMOS. The S/D tie (SDT) of this novel device circumvents short channel effect (SCEs). A double- surround-gate (the mid-gate and the spacer gate) is also presented to investigate the effect of S/D tie. According to the 2D simulation, three kinds of pseudo vertical MOSFETs are now proposed. The first one is to investigate the device characteristics of the new PTG-SDT VMOS. Our proposed structure also mitigates self-heating effect (SHEs), thereby enhancing the drain drive current and the thermal stability. Owing to its ultrathin channel (Tsi = 10 nm), the PTG-SDT VMOS has a very low subthreshold swing of 60 mV/dec, for channel lengths from 90 nm down to 40 nm. It is also found to control drain-induced barrier lowing (DIBL) and to have an excellent Gm of 4.5 mS/μm at the channel length 40 nm. The second one, we proposed the ultrathin channel pseudo tri-gate vertical MOSFET with natural source/drain tie (NSDT), the big source/drain tie (BSDT), the SDT and the without source/drain tie (WSDT) VMOS. The PTG VMOS of this novel structure circumvents short channel effects (SCEs). A new natural S/D tie (N-SDT) is also presented to investigate of the PTG VMOS. According to 2D simulation, the PTG-NSDT also show the excellent thermal dissipated such as the lattice temperature in the drain-on-top configuration and drain-on-bottom configuration were improved 47% and 66% respectively, thereby enhancing the ON-state and OFF-state current ratio. In addition, the dependence of GIDL current on body bias and temperature is characterized and discussed when the source and drain interchanged. Although the PTG VMOS keep the double-surround-gate and S/D tie structure, the design flow is more simplify even increase the drain drive current and immunity the SHEs.
目次 Table of Contents
第一章、緒論.......................1
1.1論文評論...................... 3
1.1.1垂直式金氧半場效電晶體................. 3
1.1.2矽覆絕緣金氧半場效電晶體................ 7
1.1.3結論..........................11
第二章、元件設計與製程結構................12
2.1動機........................13
2.1.1 PTG-SDT VMOS.....................13
2.1.2 PTG-NSDT VMOS....................14
2.1.3 PTG-OSDT VMOS....................15
2.2 FLOOPS TCAD 2-D 元件製程模擬與應用........16
2.2.1 PTG-SDT VMOS.....................16
2.2.2 PTG-NSDT VMOS....................18
2.2.3 PTG-OSDT VMOS....................20
2.3PTG-ONSDT VMOS實際製程.............22
2.3.1元件實作設計與考量...................22
2.3.2傳統元件設計與考量...................23
2.4結論(延伸探討與可能優點)..............24
第三章、結果與討論....................26
3.1元件製程模擬結果與物理模型應用...........26
3.1.1 PTG-SDT與設計元件結果比較.............. 29
3.1.2 PTG-NSDT與設計元件結果比較.............. 40
3.1.3 PTG-ONSDT與設計元件結果比較............. 52
3.2元件實作結果與討論.................56
3.2.1 PTG-ONSDT實作結果.................. 56
3.3結論........................63
第四章、結論.......................64
第五章、未來發展與應用..................65
5.1 具有NDR特性之1T-1IBTD SRAM memory cell應用...65
5.2 單電晶體之動態隨機存取記憶體(1T-DRAM)之應用... 67
5.3 PTG VMOS 之TFT平面顯示器應用..........72
參考文獻.........................73
附錄...........................81
A.連續製程RUNCARD說明............... 81
PTG-ONSDT & DG-ONSDT.................. 80
B.個人著作......................98
C.共同著作......................99
D.個人得獎相關文件..................101
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