在各種研究領域中，我們常使用查表法來加速硬體的效能及減少硬體的面積。本篇論文提出了幾種應用於錯誤糾正碼以及函數近似法中以查表法為主的新設計。在第三章中，我們設計了一個新的函數近似法，稱為”二階段近似法”。在這個方法中，使用piecewise的一階多項式做為第一階段的初始化逼近，接著再利用共享”正規化後的差值函數 ”來做為第二階段的進一步逼近。我們在第四章中，則透過非等份切割法，切割表格後再將表格重排，以取得可較節省面積的對應方式，此方法針對函數近似演算法加以改良，可有效減少表格面積、整體硬體面積以及額外的硬體負擔。在前面所提的函數近似法中，是使用多項式逼近法將原本的函數曲線切割成許多子區間，每個子區間再以較低階的多項式逼近，並將多項式的係數儲存於ROM中。而piecewise架構在四個部份會產生誤差，分別為多項式逼近(approximation errors)、係數量化(coefficient quantization errors)、乘法器及平方器等元件截斷(truncation errors)和最後四捨五入(rounding error)的誤差。不像傳統的piecewise架構必須事先做誤差分析，評估每個部分有多少誤差預算，再將誤差分配給每個會產生誤差的部份。因此在第五章中，本論文提出了一個新的方法，不再需要事先分配誤差給各部份，而是將上述所有誤差一併考慮，可以有效降低ROM和算術單元的面積與延遲時間。同樣，類似的查表法概念也可以被應用在錯誤糾正碼的方面。所以在第六章中，我們發展了一個以拉格朗日插值法(Lagrange Interpolation)為基礎的里德所羅門編碼器(Reed-Solomon Encoder)，此方法主要的核心概念為將修改過的拉格朗日多項式係數存在表格中以加速硬體的計算，並且達到低功率的效果。

Lookup-table (LUT)-based method is a common approach used in all kinds of research topics. In this dissertation, we present several new designs for table-based function evaluation and table-based error correcting coding. In Chapter 3, a new function evaluation method, called two-level approximation, is presented where piecewise degree-one polynomials are used for initial approximation in the first level, followed by the refined approximation for the shared normalized difference functions in the second level. In Chapter 4, we present a new non-uniform segmentation method that searches for the optimal segmentation scheme with the different design goals of minimizing either ROM, total area, or delay. In Chapter 5, a new design methodology for table-based function evaluation is presented. Unlike previous approaches that usually determine the bit widths by assigning allowable errors for individual hardware components, the total error budget of our new design is considered jointly in order to optimized the bit widths of all the hardware components, leading to significant improvements in both area and delay. Finally, in Chapter 6, the similar table-based concept is used in the design of error correcting encoder using the modified polynomial of the Lagrange interpolation formula, resulting in smaller critical path delay and lower power consumption.

中文論文審定書 i
英文論文審定書 ii
Acknowledgement（誌謝） iv
中文摘要 v
Abstract vi
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Dissertation Organization 3
Chapter 2 Survey of Related Works 4
2.1 Arithmetic Categories 4
2.1.1 Table-bound Methods 6
2.1.2 In-between Methods 12
2.1.3 Summary 26
2.2 Design of error correcting encoder 27
2.2.1 Linear Feedback Shift Register (LFSR) 28
2.2.2 Lagrange 31
Chapter 3 Table-Based Two-Level Approximation 33
3.1 Two-level Approximation 33
3.1.1 Initial Approximation 33
3.1.2 Refined Approximation 35
3.2 Hardware Architecture 37
3.2.1 Overall Hardware Architecture 37
3.2.2 Trade-off Between Two levels of Approximations 38
3.3 Error Analysis and Bit Width Optimization 39
3.4 Experimental results and comparison 40
3.5 Conclusion 44
Chapter 4 Non-uniform Segmentation for Function Evaluation with Address Re-mapping 45
4.1 Previous Uniform and Non-uniform Segmentation 45
4.2 Proposed Non-uniform Segmentation with Remapping 46
4.2.1 Address Remapping 49
4.2.2 Hardware Implementation 52
4.3 Experimental Results 54
4.3.1 Comparison of Coefficient ROM and Segment Address Encoder 54
4.3.2 Optimization of ROM, Total Area and Delay 56
4.3.3 Comparison with Hierarchical Segmentation 59
4.3.4 Trade-Off of Different Design Methods 66
4.4 Conclusions 69
Chapter 5 Hardware-Efficient Function Evaluation with Joint Error Consideration 70
5.1 Conventional Error Analysis 70
5.2 Proposed Design 72
5.2.1 Proposed Vertical Truncation Algorithm 72
5.2.2 Proposed Slanted Truncation Algorithm 79
5.3 Experimental Results 80
5.4 Conclusions 84
Chapter 6 Table-Based Design of Error Correcting Encoder 85
6.1 VLSI Design of Lagrange Interpolation Formula 85
6.1.1 Pipelined Lagrange Interpolation Architecture 88
6.1.2 Low Power Design 91
6.2 Experimental Results and Comparison 98
6.2.1 Critical Path Analysis 98
6.2.2 Experimental Results and Comparison 100
6.3 Conclusions 106
Chapter 7 Conclusions 108
7.1 Conclusions 108
7.2 Future Works 108
Bibliography 111

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