本論文提出一個分佈回饋與前饋離散時間三角積分調變器應用在無線電。我們都知道三角積分調變器使用了超取樣與量化雜訊移頻的效果，因此元件規格較為寬鬆。本篇論文主要在於說明架構上的不同與比較，使帶內信號較不受雜訊干擾，提高電路的解析度。在諧振器方面，提出了簡單的架構與少數電容的諧振器電路。
本篇論文使用了台積電0.18μm製程參數來進行模擬與實作且量測。我們的四階離散時間三角積分調變器的規格如下：輸入信號頻率為10.7MHz、取樣頻率為42.8MHz、信號頻寬為200kHz、超取樣率為107、一位元的量化器。

This paper presents a distributed feedback and feedforward of discrete-time delta sigma modulator applications in the radio. We know the delta-sigma modulator using oversampling and noise shaping technique, thus we can relax the specifications of the components. This paper described the architectural differences and compare, the in-band signal is less sensitive to noise interference, and improve the resolution of the circuit. In the resonator, a simple structure with a small number of capacitor in resonator circuit.
This paper uses the TSMC 0.18μm process parameters to the simulation, implementation, and measurement. Our fourth-order discrete-time delta-sigma modulator specifications as follows: the input signal frequency is 10.7MHz, the sampling frequency is 42.8MHz, the signal bandwidth is 200kHz, oversampling rate is 107, and one bit quantizer.

中文論文審定書 i
英文論文審定書 ii
致謝 iii
摘要 iv
Abstract v
目錄 vi
圖次 viii
表次 ix
第一章 緒論 1
1.1 介紹 1
1.2 動機 2
1.3 章節規劃 3
第二章 三角積分調變器的原理與架構 4
2.1 信號處理系統 4
2.2 三角積分調變器的基本定理 5
2.2.1 尼奎斯特與超取樣 6
2.2.2 取樣與保持(S/H) 8
2.2.3 量化誤差 9
2.3 雜訊 11
2.4 三角積分調變器的組成 12
2.5 解析連續與離散 17
2.5.1 基本組態 17
2.5.2 積分器的差別 18
2.5.3 電路誤差 20
2.5.4 時間抖動 21
2.6 架構 22
第三章 四階離散時間三角積分調變器的設計 24
3.1 雜訊傳輸函數設計 24
3.2 四階離散時間三角積分調變器的設計 27
3.3 諧振器 30
3.4 所使用的單元 34
3.4.1 全差動雙級運算放大器 34
3.4.2 共模回授 35
3.4.3 量化器 36
3.4.4 非重疊時脈產生器 37
3.4.5 加法器 38
3.4.6 偏壓電路 39
3.4.7 CMOS開關 40
第四章 模擬與量測 41
4.1 架構模擬 41
4.2 模擬結果 43
4.3 量測結果 49
4.4 文獻特性比較 50
第五章 結論 51
參考文獻 52

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