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博碩士論文 etd-0723112-203731 詳細資訊
Title page for etd-0723112-203731
論文名稱
Title
低電壓主動式電感低雜訊放大器
Low Voltage Active Inductor Low Noise Amplifier
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
59
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2012-07-06
繳交日期
Date of Submission
2012-07-23
關鍵字
Keywords
調控疊接主動式電感、早期的主動式電感、雜訊、低雜訊放大器、低電壓主動式電感
Early active inductor, Low voltage active inductor, LNA, Noise, Regulated cascode active inductor
統計
Statistics
本論文已被瀏覽 5726 次,被下載 2451
The thesis/dissertation has been browsed 5726 times, has been downloaded 2451 times.
中文摘要
本論文是利用主動式電感來代替被動式電感節省面積,輸入匹配方面利用回授電容跟電阻並聯來達到匹配跟控制輸入電壓,此外調整回授電阻可以控制雜訊。
本研究的低雜訊放大器頻寬為800MHz~2.5 GHz消耗功率為13.2mW,並且達到輸入反射損耗(S11)小於-10dB,輸出反射損耗(S22)小於-10dB,順向增益(S21)11.3~14.5dB,逆向隔離 (S12) 小於-40dB,雜訊指數3~3.18dB,1dB增益壓所點(P1dB)為-24dBm,輸入三階截距點(IIP3)為-14dBm。
Abstract
This paper is the use of the active inductor instead of passive inductors to save area, enter the match aspects of the use of the feedback capacitor in parallel with the resistor to achieve matching with the control input voltage, in addition to adjusting the feedback resistor can control the noise.
The LNA dissipates 13.2 mW power and achieves input return loss (S11) below -10dB, output return loss (S22) below -10 dB, forward gain (S21) of 11.3~14.5dB, reverse isolation (S12) below -40dB, and noise figure (NF) of 3~3.18 dB. 1-dB compression point (P1dB) of -24 dBm and input third-order inter-modulation point (IIP3) of -14 dBm .
目次 Table of Contents
致謝 iii
摘要 iv
Abstract v
目錄 vi
圖次 vii
表次 viii
第一章 導論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文架構 2
第二章 低雜訊放大器的設計 3
2.1 射頻低雜訊放大器的基本面 3
2.2 雜訊 3
2.2.1 通道熱雜訊 4
2.2.2 閃爍雜訊 5
2.2.3 分佈式柵極電阻雜訊 6
2.2.4 感應閘極電流雜訊(Induced gate current noise) 6
2.3 常用低雜訊放大器 8
2.3.1 電感退化性(Inductive Degeneration) 8
2.3.2 並串回授(shunt-series feedback) 14
第三章 主動式電感的分析 16
3.1 被動式電感器的簡介 16
3.2 主動電感的分析 18
3.2.1 早期的主動式電感 18
3.2.2 調控疊接主動式電感(Regulated cascode active inductor) 20
3.2.3 基本迴轉(gyrator)元件 26
3.2.4 低電壓主動式電感 28
第四章 論文電路架構 30
4.1 主動式電感 31
4.2 增益 33
4.3 輸入阻抗 34
4.4 輸出阻抗 36
4.5 雜訊 37
第五章 模擬結果與量測結果 40
5.1 模擬結果 40
5.2 量測結果與討論 47
第六章 結論 48
References 49
參考文獻 References
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[18]M. M. Reja, K. Moez, and I. Filanovsky, “An area-efficient multistage 3.0- to 8.5-GHz CMOS UWB LNA using tunable active inductors,” IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 57, no. 8, pp. 587–591, Aug. 2010.

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