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博碩士論文 etd-0723117-102916 詳細資訊
Title page for etd-0723117-102916
論文名稱
Title
具有凹槽式閘極與本體延伸層的穿隧場效電晶體電性分析
Characteristics of Recessed-Gate TFETs with Body Extension Layer
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
115
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2017-07-27
繳交日期
Date of Submission
2017-08-23
關鍵字
Keywords
開啟關閉電流比、互補式穿隧場效反相器、雜訊邊界、次臨界擺幅、穿隧場效電晶體、矽覆絕緣、反摻雜、線穿隧
CTFET, noise margin, on off current ratio, subthreshold swing, line tunneling, counter-doped, SOI, tunneling field transistor
統計
Statistics
本論文已被瀏覽 5660 次,被下載 57
The thesis/dissertation has been browsed 5660 times, has been downloaded 57 times.
中文摘要
在此篇論文中我們提出一具有凹槽式閘極與本體延伸層的穿隧場效電晶體,利用凹槽式的閘極與本體延伸層間的線穿隧機制,大幅增加穿隧面積,以增加元件的開啟電流。利用反摻雜(Counter-Doped)的凹槽式本體延伸層近一步的增加元件的開啟電流。我們所提出之具有凹槽式閘極與本體延伸層的穿隧場效電晶體,在外加偏壓VD = 0.5 V 下,可達到開啟電流1.44 × 10-6 A/μm且開啟關閉電流比達3.22 × 109,達到了最小次臨界擺幅28.3 mV/dec與橫跨7個數量級(orders)汲極電流範圍的平均次臨界擺幅59.8 mV/dec。而本論文所提出之正型穿隧場效電晶體(pTFET),在外加偏壓VD = -0.5 V 下,可達到開啟電流9.86 × 10-7 A/μm與3.86 × 109的開啟關閉電流比,達到27.4 mV/dec的最小次臨界擺幅和橫跨8個數量級(orders)汲極電流範圍的平均次臨界擺幅54.9 mV/dec。而我們所提出之穿隧場效互補式反相器,在供應電壓VDD = 0.5 V時,低與高電位雜訊邊界(Noise Margins, NMs)分別為NML = 201 mV與NMH = 219 mV,分別佔了供應電壓VDD的40.2 %與43.8 %。而當供應電壓微縮至VDD = 0.2 V時,低與高電位雜訊邊界分別為NML = 65 mV與NMH = 77 mV,佔了供應電壓VDD的32.5 %與38.5 %。
Abstract
In this paper we propose a recessed-gate tunneling field transistor to improve the ON current of TFET by increasing the tunnel area with line tunneling. We investigate the effects of the body extension layer thickness and the doping level on the device performance. For optimal device structures, our proposed n-TFET reaches 1.44 × 10-6 A/μm of ON current and 3.22 × 109 ON/OFF current ratio. A minimum subthreshold swing SSmin = 28.26 mV/dec and an average swing SSavg = 59.8 mV/dec over 7 orders of drain current are achieved. For our proposed p-TFET, 9.86 × 10-7 A/μm of ON current and 3.86 × 109 of ON/OFF current ratio are achieved. The SSmin = 27.4 mV/dec and an SSavg = 54.9 mV/dec over 8 orders of drain current are achieved. The low-level noise margin NML = 201 mV and high-level noise margin NMH = 219 mV are obtained from our proposed CTFET interter under VDD = 0.5 V, which occupy 40.2 % and 43.8 % of applied voltage. With supply voltage scaling to VDD = 0.2 V the NML = 65mV and NMH = 77mV are obtained which is about 32.5 % and 38.5 % of the VDD.
目次 Table of Contents
中文審定書 i
英文審定書 ii
致 謝 iii
摘 要 iv
Abstract v
目 錄 vi
圖目錄 viii
表目錄 xiv
第一章 導論 1
1.1 研究背景 1
1.1.1 改變架構 4
1.1.2 閘極工程 8
1.1.3 改變材料 12
1.1.4 陡接面技術 15
1.2 動機 17
第二章 物理機制與元件操作原理 19
2.1 元件物理機制 19
2.1.1 穿隧場效電晶體(TFET)物理與操作機制 19
2.2 邏輯元件操作理論與原理 22
2.2.1 傳統互補式金氧半邏輯閘操作理論與原理 22
2.2.2 凹槽式閘極穿隧電晶體所構成之互補式穿隧場效反相器 26
第三章 元件架構設計與製程步驟 29
第四章 電性討論與分析 32
4.1 元件模擬使用之物理模型說明 32
4.2 元件模擬結果分析與討論 32
4.2.1 凹槽式負型穿隧場效電晶體 33
4.2.2 凹槽式本體延伸層在凹槽式閘極之負型穿隧場效電晶體架構之研究 42
4.2.3 線穿隧與點穿隧在凹槽式閘極之負型穿隧場效電晶體架構之研究 50
4.2.4 線穿隧面積大小在凹槽式負型穿隧場效電晶體電性分析 53
4.2.5 能陷輔助穿隧機制在凹槽式負型穿隧場效電晶體之電性分析 58
4.2.6 凹槽式正型穿隧式場效電晶體 67
4.2.7 具凹槽式閘極與本體延伸層穿隧電晶體與其他文獻穿隧電晶體比較 76
4.3 具有凹槽式閘極與本體延伸層之互補式穿隧場效反相器電性分析 77
4.4 元件實作與量測結果 82
第五章 結論與未來展望 87
5.1 結論 87
5.2 未來展望 88
參考文獻 89
附錄 97
論文著述 100
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