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博碩士論文 etd-0724106-144647 詳細資訊
Title page for etd-0724106-144647
論文名稱
Title
可變執行長度迴圈之效能與能量最佳化技術
Performance and Energy Optimization Techniques for Loops with Variable Execution Length
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
77
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2006-07-14
繳交日期
Date of Submission
2006-07-24
關鍵字
Keywords
迴圈、可變執行長度、能量、效能
Loop, Variable Execution Length, Performance, Energy
統計
Statistics
本論文已被瀏覽 5669 次,被下載 11
The thesis/dissertation has been browsed 5669 times, has been downloaded 11 times.
中文摘要
大多數對迴圈或巢狀迴圈的效能改善通常都是透過在編譯時間已知的迴圈執行長度來進行做管線化排程(pipelined scheduling),但是對於在編譯時間未知執行長度的迴圈卻沒有多加著墨。在這篇論文中,我們提出了一個以常見案例(Common-Case)為基礎的方法來改善迴圈效能,並且利用模數排程(Modulo schedule)在符合資源限制和不違反資料相依性的情況下來達到可變執行長度迴圈做管線化排程的目標。我們所提出的常見案例方法,不僅有效的減少了執行的時間,並且由於執行時間大量減少使得能量的消耗也大量的減少,透過尋找良好的常見案例方式確實可以對那些在編譯時間未知執行長度的迴圈提供一個良好的解決方式,然後再藉由時脈閘控(Clock-Gating)的技術和分解有限狀態機(Finite State Machine decomposition)的方法更進一步降低能量消耗。
最後,我們將所提出的常見案例的方法應用到三個實際的例子(Morris-Pratt Algorithm, Insertion Sort, Running Length Encoding)來證明我們的方式和流程是正確並且能有效的達成效能與能量最佳化的目標。
Abstract
In most techniques to improve performance for loops or nested loops, they are often to do pipelined scheduling according to know loop execution times at compiler time. But it is hardly to pipeline the execution of loop whose execution length is unknown before loop execution at compiler time. In this thesis, a Common-Case based approach is proposed to improve the performance of loops with variable execution length. Besides, we use the modulo schedule to achieve the goal under resource constraint and without violating data dependence. The Common-Case approach not only reduces the execution time efficiently, but also reduces the power consumption largely due to the reduction of execution time. Through the searching for good Common-Case, we can surely supply a better solution to the loops whose execution length is unknown before loop execution at compiler time. Moreover, since the loop is divided into Common-Case and exception parts, we can further reduce power consumption by using Clock-Gating and Finite State Machine decomposition techniques.
Finally, experiments on three real examples (Morris-Pratt Algorithm, Insertion Sort, Running Length Encoding) are used to demonstrate that our flow is correct and can achieve the goal of performance and energy optimizations.
目次 Table of Contents
1 Introduction
2 Basic Principle
2.1. Problem Description
2.2. Common-Case Computation
2.3. Modulo Scheduling
2.3.1. Overview
2.3.2. Motivating Example
3 The Proposed Approach
3.1. Common-Case Selection
3.1.1. Behavior (Algorithm) Domain
3.1.2. Instruction Domain
3.1.3. Selecting Rule
3.2. Loop Pipeline
3.2.1. Loop Dependence
3.2.2. Single Loop Pipeline
3.2.3. Pipeline Use Modulo Schedule
3.2.4. Shift Register
3.3. Single Loop Pipeline With Multiple Exits
3.4. Datapath Construction
3.4.1. Basic ideas
3.4.2. Resource Sharing
3.4.2.1. Storage Element Sharing
3.4.2.2. Function Unit Sharing
3.5. Energy Optimization
3.5.1. RTL Clock Gating
3.5.1.1. Central Clock gating
3.5.1.2. Distributed Clock Gating
3.5.1.3. Clock Gating plan
3.5.2. Datapath control
3.5.2.1. Finite State Machine Decomposition
4 Experiment Results
5 Conclusion and Future Work
參考文獻 References
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[13] Roberto Zafalon, Andrea Veggetti, Roberta Buger, “New Clock Gating Feature in Power Compiler v1999.05”, SUNG 1999.
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Digital Object Identifier 10.1109/MICRO.1995.476818
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