本論文有兩大主題：FlexRay車載網路通信系統實體層設計與高速32位元樹狀架構之進位前瞻式加法器兩大部分。
第一部分介紹FlexRay車載網路通信系統之系統規範，以及將FlexRay車載網路通信系統之實體層部分以單一個系統單晶片予以實現。
第二部分利用我們提出互補式全N電晶體(Complement All-N-Transistor, CANT)架構，並組成一個樹狀架構之前瞻進位式加法器。我們利用動態偏壓的方式加快反相動態電路轉態速度，使得反相與非反相電路的運作速度極為相近。本加法器架構具有容易擴充資料架構之優點，且以UMC 90 nm製程設計與實現，本晶片工作時脈速度可達7.2 GHz。

This thesis comprises two parts : the first one is the design and implementation of FlexRay automotive communication system physical layer; the second part is the design of a high speed pipelined tree-structured carry lookahead adder (CLA).
The first part of this thesis is to introduce the physical layer specification of FlexRay automotive communication system. Then, it is realized in an SOC by a typical 0.18 um CMOS process.
The second topic is to propose a novel CANT logic. By the CANT logic, a pipelined tree-structured carry lookahead adder is designed and implemented. The dynamic bulk biasing technique is utilized to increase the switching speed of inverting circuits such that the delays of the inverting and non-inverting circuit is very close. The proposed architecture can be easily expanded to long data words CLA. Post-layout simulations reveal that the 32-bit CLA using the proposed CANT logic can operate up to 7.2 GHz by using the UMC 90 nm process.

致謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vii
表目錄 x
第一章 概論 1
1.1 研究動機 1
1.1.1 FlexRay車載網路通信系統 1
1.1.2 樹狀架構之前瞻進位式加法器 2
1.2 相關技術與文獻探討 3
1.2.1 FlexRay車載網路通信系統實體層晶片設計 3
1.2.2 樹狀架構之進位前瞻式加法器 4
1.3 論文大綱 7
第二章 FlexRay車載網路通信系統實體層晶片設計 8
2.1 簡介 8
2.2 FlexRay系統實體層原理與架構 10
2.2.1 匯流排驅動器 (Bus Driver) 10
2.2.2 匯流排仲裁器 (Bus Guardian) 11
2.2.3 匯流排仲裁器之通信排程 13
2.2.4 信號監測電路 (Watchdog) 18
2.3 實體層電路設計 21
2.3.1 匯流排驅動器 21
2.3.2 匯流排仲裁器 27
2.4 電路模擬與晶片量測 33
2.4.1 電路模擬結果 33
2.4.2 晶片實作與量測結果 37
2.5 討論 40
第三章 樹狀架構之進位前瞻式加法器 41
3.1 簡介 41
3.2 原理與架構說明 42
3.2.1 互補式全N電晶體邏輯 (CANT Logic) 43
3.2.2 傳播與產生信號單元 49
3.2.3 五階進位產生陣列 50
3.2.4 總和單元 55
3.3 晶片電路設計 56
3.3.1 時脈同步問題 57
3.3.2 虛擬亂數產生器 (PRNG) 58
3.3.3 環型震盪器 59
3.4 電路模擬 60
3.5 結論 62
第四章 結論 63
參考文獻 65

[1] Flexray Communications System Electrical Physical Layer Specification, Ver. 2.1.
[2] Flexray Communications System Bus Guardian Specification, Ver. 2.0.
[3] TJA1080 FlexRay transceiver, Rev. 02, Jul. 12, 2007. (http://www.nxp.com/acrobat/datasheets/TJA1080_2.pdf)
[4] G. Caruso, “FlexRay Transceiver in a 0.35um CMOS High-Voltage Technology,” Design, Automation and Test in Europe 2006 (DATE ’06), vol. 2, pp. 1-5, Mar. 2006.
[5] A. Techmer, and P. Leteinturier, “Implementing FlexRay on Silicon,” Proceedings of the International Conference on Networking, International Conference on Systems and International Conference on Mobile Communications and Learning Technologies, 2006 (ICNICONSMCL ’06), pp. 34-40, Apr. 2006.
[6] P. M. Szecowka, and M. A. Swiderski, “On hardware implementation of flexray bus guardian module,” International Conference on Mixed Design of Integrated Circuits and Systems 2007 (MIXDEX ’07), pp. 309-312, Jun.2007.
[7] R. X. Gu, and M. I. Elmasry, “All-N-logic high-speed true-single-phase dynamic CMOS logic,” IEEE J. Solid-State Circuits, vol. 31, no. 2, pp. 221-229, Feb. 1996.
[8] Z. Wang, G. A. Jullian, W. C. Miller, J. Wang, and S. S. Bizzan,
“Fast adders using enhanced multiple-output domino logic,” IEEE J. Solid-State Circuits, vol. 32, no. 2, pp. 206-214, Feb. 1997.
[9] J. Yuan, and C. Svensson, “High-speed CMOS circuit technique,” IEEE J. Solid-State Circuits, vol. 24, no. 2, pp. 62-70, Feb. 1989.
[10] C. M. Lee, and E. W. Szeto, “Zipper CMOS,” IEEE Circuits and Devices Mag., pp. 10-16, May 1986.
[11] Y. Ji-Ren, I. Karlsson, and C. Svensson, “A true single-phase-clock dynamic CMOS circuit technique,” IEEE J. Solid-state Circuit, vol. 22, no. 5, pp. 899-901, Oct. 1987.
[12] 黃振榮，“應用於數位信號處理之高速基本算數元件硬體實作”，中山大學電機工程學系博士論文，民國八十九年五月。
[13] C.-C. Wang, C.-J. Huang, and K.-C. Tsai, “A 1.0 GHz 0.6-um 8-bit carry lookahead adder using PLA-styled all-N-transistor logic,” IEEE Trans. Circuit and Systems, Part II: Analog and Digital Signal Processing, vol. 47, no. 2, pp. 133-135, Feb. 2000.
[14] 蔡坤助，“前瞻性微處理機之以PLA形式全N電晶體邏輯設計之1.0 GHz 0.6um前看進位加法器與64-bit平行比較器”，中山大學電機工程學系博士論文，民國八十七年六月。
[15] R. P. Brent, and H. T. Kung, “A Regular Layout for Parallel Adders,” IEEE Trans. on Computers, vol. C-31, no. 3, pp. 1209-1211, Mar. 1982.
[16] G. Yang, S. O. Jung, K. H. Baek, S. H. Kim, S. K. Kim, and S.M. Kang, “A 32-Bit Carry Lookahead Adder Using Dual-Path All-N Logic,” IEEE Trans. on Very Large Scale Integration Systems, vol. 13, no. 8, pp. 992-996, Aug. 2005.
[17] C.-C. Wang, Y.-L. Tseng, P.-M. Lee, R.-C. Lee, and C.-J. Huang, “A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic,” IEEE Trans. Circuit and Systems, Part I: Circuits and Systems, vol. 50, no. 9, pp. 1208-1215, Sep. 2003.
[18] W. Elgharbawy, and M. Bayoumi, “New bulk dynamic threshold NMOS schemes for low-energy subthreshold domino-like circuits,” IEEE Computer Society Annual Symposium on VLSI, pp. 115-120, Feb. 2004.
[19] W. Elgharbawy, and M. Bayoumi, “B-DTNMOS: a novel bulk dynamic threshold NMOS scheme,” International Symposium on Circuits and Systems, vol. 2, pp. 413-416, May 2004.
[20] K. Wu, S. Jia, Z. J. Chen, and X. W. Gan, “Implementation of low-voltage true-single-phase-clocking (TSPC) logic using bulk dynamic threshold MOS technique,” International Conference on ASIC, vol. 1, pp. 158-162, Oct. 2005.
[21] G.-N. Sung, C.-Y. Juan, and C.-C. Wang, “Bus Guardian Design for Automobile Networking ECU Nodes Compliant with FlexRay Standards,” International Symposium on Consumer Electronics, 2008 (ISCE ’08), CD-ROM version, Networking I, Apr. 2008.
[22] G.-N. Sung, C.-Y. Juan, and C.-C. Wang, “A 32-bit carry lookahead adder design using complementary All-N-Transistor logic,” International Conference on Electronics, Circuits, and Systems, 2008 (ICECS ’08), Paper ID: 4485, accepted, Aug. 2008.