IC設計的流程包含了布林方程式的化簡，為了減少相對應的電路面積，我們必需在化簡的程序中盡可能的將布林方程式化簡。在一般的布林方程式化簡中，最主要的步驟是先將布林方程式化為SOP(Sum Of Product)的形式，再利用各種演算方法針對SOP格式的布林方程式化簡。針對SOP布林方程式格式的主要化簡方法分為two-level和three-level的化簡方式，尤以three-level化簡所得的結果更佳。今我們以找出適當的共用式的方法，將其應用在布林方程式化簡上，藉由取出共用的電路，使電路的面積、時間及電源消耗上的成本能夠得到有效的改善。同時，在一般邏輯電路合成的流程上，若能將布林方程式化簡完後同時程式能夠立即產生可合成的硬體描述語言檔案，減少額外撰寫硬體描述語言程式的動作，將能有效的節省在設計上的時間。本論文提出十種布林方程式共用式消除的方法，配合簡易的操作，能快速的產生所需的可合成硬體描述語言檔案，檔案再經由Synopsys EDA Tool合成後，可得到十一種結果(面績、時間)，由各種結果的效能考量我們可以由其中挑選出最合適的電路。另外配合本論文的方法，我們實作出AES(Advanced Encryption Standard)的晶片，並經過詳細的驗証，確認晶片功能正確並可以正常運作，由晶片實作的結果得知，使用我們的演算法實作AES晶片，在電路的面積上能獲得有效的改善。在數位訊號處理的數位濾波器，有限場多項式乘法應用中的密碼學演算法AES(Advanced Encryption Standard)，及錯誤更正碼(Error Correcting Code)中，我們可以把三種應用最後所呈現的結果以布林方程式的形式表示(AND-XOR)，然後應用取公因式的化簡方法在每一個方程式上，同樣地也可以有效的減少其電路面績及功率消耗。

The constant matrix multiplication is one of the key operations in many applications including digital signal processing, communication, and coding. In general, constant matrix multiplication can be expressed as bit-level Boolean functions. Then, common subexpression elimination (CSE) can be used to reduce the area cost of realizing these bit-level functions by finding the shared common factors among these bit-level equations. The proposed circuit generator performs logic reduction on the input Boolean functions and produces the simplified Verilog HDL codes as output. Then the simplified code is fed into Synopsys Design Compiler for further logic minimization and technology mapping to generate gate-level netlists. In this thesis, we present ten different CSE algorithms for logic reduction of the bit-level Boolean functions. The comparisons include both the architecture-level technology-independent results and the Synopsys synthesized technology-dependent results. According to the experiments, we observe that our CSE can effectively reduce the area cost. We also apply the CSE to the design of the Advanced Encryption Standard (AES) in cryptography.

中文摘要 I
Abstract II
目 錄 III
圖目錄 V
表目錄 VI
第一章、導論 1
1.1 研究動機 1
1.2 內容大綱 1
第二章、邏輯化簡相關研究 2
2.1 Synopsys的邏輯化簡方法 2
2.2 一般邏輯化簡 4
2.3 Paar的公因式消去法 6
2.4 CSE演算法在多重常數乘法上的應用 8
第三章、演算法與程式實作 11
3.1 邏輯運算表示法 11
3.2 公因式消去演算法 12
3.2.1 水平起始化簡 12
3.2.1.1 取最大漢明指標行對 13
3.2.1.2 取最小行標關連 14
3.2.1.3 取【w(i) + w(j)】總數最少 14
3.2.1.4 考量次高漢明指標的行對 15
3.2.2 垂直起始化簡 15
3.2.3 二回合式(2-round) 16
3.2.4 垂直化簡挑選省最多面積(公因式個數不限) 17
3.2.5 垂直化簡挑選省最多面積(公因式個數為2n) 18
3.2.6 垂直化簡選最大漢明指標(fanout數大於1) 18
3.2.7 垂直化簡選最大漢明指標(fanout數大於1且公因式個數為2n) 18
3.2.8 水平化簡挑選省最多面積(公因式個數不限) 18
3.2.9 水平化簡挑選省最多面積(公因式個數為2n) 19
3.2.10 水平化簡選最大漢明指標 19
3.2.11 各種演算法綜合說明 19
3.3 計算方程式的延遲時間(delay time) 20
3.4 實作流程 22
3.5 程式輸入、輸出規格 23
3.6 程式介面說明 24
第四章、實作應用與數據分析、比較 26
4.1資料加密理論(Advanced Encryption Standard) 26
4.2 實驗結果分析 29
4.2.1 不經由Synopsys Design Compiler化簡 29
4.2.2 經由Synopsys Design Compiler化簡 36
4.3 實驗討論 38
第五章、AES晶片實作 40
5.1 AES簡介 40
5.2 AES硬體架構 40
5.3 晶片實作過程與結果 41
5.3.1 使用CSE演算法化簡 42
5.3.2 設計流程 43
5.3.3 AES的硬體實現 44
5.3.4 AES功能証驗 47
5.4 結果比較 50
第六章、其他應用及未來工作 51
6.1 數位訊號處理器(FIR Filter) 51
6.2 Reed Solomon Codes 51
6.2 ISCAS Benchmark Circuits 52
6.3 設計流程整合 53
6.4 未來工作 54
參考文獻 55
附錄 58
測試檔範例 58
利用Synopsys Design Compiler轉換成GTECH所需的Script file 60

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