由於半導體製程的日益進步，為了建構高效能的積體電路，元件的尺寸愈縮愈小，配合元件縮小及所增加的內連線(Interconnects)，超大型積體電路技術所採用多層金屬導體連線的設計。然而，隨著金屬導線層的數目增加及導線間的距離不斷縮小，電子訊號在金屬連線間傳送時，由於金屬連線內連線間的電阻-電容延遲(RC delay），半導體元件速度無法提升。為了降低訊號傳遞的時間延遲，現今的發展是以較低電阻的金屬銅（電阻率為1.7μΩ-cm）來取代金屬鋁（電阻率為2.7μΩ-cm）成為導線的連線系統，以及降低電容，採用低介電（low-k）材料取代二氧化矽（SiO2）。
由於元件封裝過程中會產生的機械應變，本論文探討了元件受機械應變後的電容變化與漏電流機制。本論文探討具有金屬-絕緣體-金屬 (Metal-Insulator-Metal,MIM)結構的導線元件電容與漏電流變化機制。其中OSG(Organosilicate glass)層的低介電材料為含氧碳化矽膜(SiCO)，及量測電性用的元件結構為梳狀結構銅金屬導線。為了讓元件產生應變，利用外界機械應力來彎曲試片。選擇以不同曲率半徑模具，使得試片做不同程度之彎曲形變，與未受機械應力之試片結果比較，分析在高溫的環境下之I-V與C-V特性。
本論文研究發現，受機械應力之樣品漏電機制方面並無明顯變化，但在E1/2超過1800 V/cm1/2高電場時，同時具有Schottky與Poole Frenkel兩種漏電機制共存的現象，兩種機制同時存在於樣品中；在高溫時，Poole Frenkel漏電機制會加強。
在室溫時，隨著張應力增加電容值會下降，壓應力增加時，電容值會上升。利用文獻公式可算出元件受到外加機械應力時能障改變量，與文獻是有相同趨勢，受到張應力時能障變小，受壓應力時能障變大。在樣品之活化能變化部分也有相同之趨勢。

In order to construct the integrated circuit with high efficiency, the size of the semiconductor devices becomes smaller and smaller. The surface of the chip is unable to offer enough area for devices interconnecting, that the Ultra Large Scale Integration (ULSI) has to adopt the construction of multilayer metal conductor line, and to decrease it’s connects. However, the RC delay time becomes a main issue to limiting semiconductor speed when the electron signal was transferred between two metal connects. In order to solve the problem of RC delay, and to lower resistivity, copper (1.7 μΩ-cm) is applied instead of Aluminum (2.7 μΩ-cm) at present. In
additation, to lower the capacitance, the low-k material has taken place SiO for
reducing the electric capacity.
In this work, the capacitance and current of MIM(Metal-Insulator-Metal) of
interconnecting circuit were investigated under bending stress. SiOC of OSG
(Organic silicate glass) layer has applied to a MIM structure. In order to apply the
strain in devices, the device was bended to a fixed curvature for compressed and
tensile stress. By bending the device, the capacitance and leakage current I-V & C-V
were analyzed and compared with the unstressed SAMPLE of I-V and C-V at high
temperature, too.
The result reveals both of Schottky and Poole-Frenkel conduction mechanism
existing in device under a high electric field of 1800 V/cm1/2, which indicates the
theoretical treatment is unappropriate for the interpretation of the leakage current
mechanism.

致謝 I
中文摘要 II
ABSTRACT III
目錄 IV
圖目錄 VI
表目錄 X
第一章 緒論 1
1.1 背景 1
1.2 多層導體連線製程 3
1.3 鑲嵌結構製程 4
1.3.1 優先溝渠(Trench First)製程 5
1.3.2 優先管洞 (Via First)製程 6
1.3.3 自我對準式(Self-Aligned)製程 7
1.4 研究動機 7
第二章 基礎理論 9
2.1 漏電機制 9
2.1.1 歐姆電流（Ohmic Current） 9
2.1.2 蕭基發射(Schottky emission) 10
2.1.3 普爾-法蘭克(Pool-Frenkel)效應 11
2.1.4 空間電荷限制電流（Space-Charge Limited Current） 13
2.2 外加應力對能障影響 14
第三章 實驗儀器量測原理與實驗步驟介紹 15
3.1 試片金屬層結構與尺寸參數 15
3.2 研磨實驗步驟 15
3.3 室溫基板彎曲量測： 16
3.3.1. 升溫基板彎曲量測： 17
第四章 結果與討論 18
4.1 受機械應力下之室溫I-V特性 18
4.1.1 SD樣品室溫I-V特性 18
4.1.2 DD樣品室溫I-V特性 19
4.2 室溫下彎曲應力對電容之影響 21
4.2.1 SD樣品室溫下之電容特性 21
4.2.2 DD樣品室溫下之電容特性 23
4.3 受機械應力下之室溫漏電機制 26
4.4 變溫對電性之影響 27
4.5 複合漏電機制探討 30
第五章 結論 33
第六章 參考資料 35
附錄一 70
附錄二 72

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