在此論文中，我們提出了擁有自我對齊且具有阻隔氧化層與本體縛點之金氧半場效電晶體與非揮發性記憶的結構。
在金氧半場效電晶體方面，我們企圖以阻隔氧化層來抑制電荷共享效應，減低在微縮時短通道效應對電晶體所造成的影響，並以阻隔氧化層來阻擋閘極與源�汲極間的空乏區向通道部分擴散，減少漏電流與功率消耗的損失；而本體縛點之結構則能有效改善電晶體之溫度，降低自我加熱效應之問題產生。結果發現，具有阻隔氧化層與本體縛點之電晶體結構確實擁有不錯的特性，如小的 DIBL 、較傾斜的次臨限斜率、以及高的電流On / Off比等特性，以應證能降低短通道效應之影響。
在非揮性記憶體方面，由於傳統的 SONOS 閘極穿透氧化層（Tunneling oxide）厚度太薄，在低於三奈米時會使得通道上的電洞因為直接穿透（Direct tunneling）至氮化矽，使得穿透進來的電洞與氮化矽內部捕陷層（Trap layer）的電子產生中和進而使記憶體內部的資料消失而產生漏電的現象，造成資料保存時間下降（Data retention）或是資料可寫入的次數（Endurance）減少；然而如果為了改善其漏電的現象而將穿透氧化層厚度增厚，反而會使得能障提高，造成抹除速度下降。因此在結構上，我們企圖在基板上引入本體縛點與阻隔氧化之層結構，並在不減少閘極穿透氧化層的厚度以及不改變閘極結構與材料的情況下，能有更優越的閘極控制力，增加開關電流比（On / Off ratio），擁有較陡峭的次臨界導通斜率SS（subthreshold slope），使得元件在進入寫入�抹除（Program�Erase）的操作時，能具有更高的效率，比一般標準結構的SONOS能更為穩定，增加元件的可靠度與穩定性。

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第一章 導論 -------------------------------------------------- 7
1-1矽覆絕緣金氧半場效電晶體簡介------------------------------ 7
1-2非揮發性記憶體簡介---------------------------------------- 11
第二章 元件設計與製程 ----------------------------------------- 18
2-1元件設計-------------------------------------------------- 18
2-1-1 具有阻隔氧化層與本體縛點之金氧半場效電晶體
（bSPIFET） --------------------------------------- 18
2-1-2具有阻隔氧化層與本體縛點之非揮發性記憶體
（bSPISONOS）------------------------------------- 20
2-2元件ISE TCAD FLOOPS 2-D模擬設計------------------------- 22
2-2-1具有阻隔氧化層與本體縛點之金氧半場效電晶體
（bSPIFET）---------------------------------------- 23
2-2-2具有阻隔氧化層與本體縛點之非揮發性記憶體
（bSPISONOS）------------------------------------- 25
2-3實際製程 ------------------------------------------------ 25
2-3-1實際製程考量------------------------------------------- 28
2-3-2實際製程----------------------------------------------- 30
第三章 結果與討論 -------------------------------------------- 32
第四章 結論 -------------------------------------------------- 51
第五章 未來發展 ---------------------------------------------- 52
參考文獻 ----------------------------------------------------- 53
附錄 :
圖目錄

圖 1.1：bFDSOI之結構示意圖 --------------------------------- 09
圖 1.2：Re S/D UTBSOI之結構示意圖 -------------------------- 10
圖 1.3：PiFET之結構示意圖 ---------------------------------- 10
圖 1.4：浮動閘極元件與電荷能陷儲存元圖 ---------------------- 12
圖1.5：浮動閘極元件耦合干擾 --------------------------------- 13
圖1.6：過薄的穿透氧化層造成漏電 ----------------------------- 13
圖1.7：SONOS memory結構示意圖 ----------------------------- 14
圖 1.8：Twin-SONOS之結構示意圖 ----------------------------- 15
圖 1.9：TANOS之結構示意圖 -------------------------------- 16
圖 1.10：BE-SONOS之結構示意圖 ------------------------------ 17
圖 2.1：bSPIFET的元件結構示意圖------------------------------ 19
圖 2.2：bSPISONOS的元件結構示意圖--------------------------- 21
圖 2.3：bSPIFET使用ISE TCAD FLOOPS軟體模擬簡易製程步驟圖--- 24
圖 2.4：bSPISONOS使用ISE TCAD FLOOPS軟體模擬簡易製程步驟圖 27
圖 2.5：實際製程之重要流程步驟--------------------------------- 29
圖 2.6：實際製程之主要步驟流程圖 ------------------------------ 31
圖 3.1：bSPIFET與對照組元件的切面圖 -------------------------- 33
圖 3.2：bSPIFET與對照組元件的輸入特性曲線--------------------- 33
圖 3.3：bSPIFET與對照組元件的臨限電壓特性圖-------------------- 35
圖 3.4：bSPIFET與對照組元件的臨限電壓特性圖-------------------- 35
圖 3.5：bSPIFET與對照組元件的DIBL特性圖---------------------- 36
圖 3.6：bSPIFET與對照組元件的輸出特性曲線---------------------- 36
圖 3.7：bulk MOSFET在VGT=0.2V的晶格溫度分佈圖---------------- 38
圖 3.8：bSPIFET在VGT=0.2V的晶格溫度分佈圖--------------------- 38
圖 3.9：UTBSOI在VGT=0.2V的晶格溫度分佈圖--------------------- 39
圖 3.10：bulk MOSFET在VGT=0.2V的碰撞游離數目分佈圖------------40
圖 3.11：bSPIFET在VGT=0.2V的碰撞游離數目分佈圖---------------- 40
圖 3.12：UTBSOI在VGT=0.2V的碰撞游離數目分佈圖---------------- 41
圖 3.13：bSPIFET與對照組元件的串聯電阻特性圖------------------- 42
圖 3.14：不同的阻隔氧化層高度的電性圖--------------------------- 42
圖 3.15：L-Edit之光罩圖---------------------------------------- 43
圖 3.16：電子顯微鏡檢視圖-------------------------------------- 45
圖 3.17：光學顯微鏡檢視圖-------------------------------------- 45
圖 3.18：bSPIFET之穿透式電子顯微鏡（TEM）元件剖面圖---------- 46
圖 3.19：bSPISONOS之穿透式電子顯微鏡（TEM）元件剖面圖-------- 46
圖 3.20：4156量測時之簡圖---------------------------------------47
圖 3.21：線性區輸入特性曲線IDS-VGS ------------------------------48
圖 3.22：線性區轉導特性曲線------------------------------------- 48
圖 3.23：飽和區輸入特性曲線IDS-VGS------------------------------ 49
圖 3.24：輸出特性曲線IDS-VDS------------------------------------ 49
圖 3.25：不同溫度下的線性區輸入特性曲線IDS-VGS ------------------ 50
圖 3.26：不同溫度下的線性區轉導特性曲線------------------------- 50

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