在無線通訊系統上，迴旋碼是目前最流行的錯誤更正碼。為了防止傳輸時的雜訊干擾，傳送端通常會採用迴旋碼(Convolution code)將傳送資料進行編碼，而接收端則使用維特比解碼器(Viterbi decoder)進行解碼並且更正錯誤位元以達到降低位元錯誤率(Bit error rate)。在3G行動通訊中，基地台與通訊裝置之間經常使用此種解碼器作為解碼的機制。在行動通訊裝置上，由於傳統解碼器的功率消耗占整個訊號接收器的三分之一以上，因此在行動通訊系統上，如何有效率地減少維特比解碼器的功率消耗，就成了本論文研究的重點。
傳統的迴旋編碼器所採用的是歸零收尾方式(Zero -tail)。這種編碼方式具有較佳的抗雜訊干擾能力，但這個做法會增加額外的收尾位元(Tail bit)，而額外增加的收尾位元會造成碼率(Code rate)下降以及影響傳輸的效率，尤其對於長度較短資料的影響會更加明顯，例如封包的檔頭(Header)。去尾迴旋碼(Tail-biting convolution code)是另一種錯誤更正碼，能夠保持碼率(Code rate)不變，且近年來逐漸被用於長期演進(LTE)的控制通道。但是去尾迴旋碼(Tail-biting convolution code)解碼器比傳統的解碼器更複雜，因此本論文修改Wrap-Around Viterbi Algorithm (WAVA)以降低迭代(iteration)次數，達到保持位元錯誤率不變的效果，並且大幅降低功率消耗以及保持解碼的正確性。
除此之外，若收到的資料沒有受到雜訊干擾，則不必進入去尾迴旋解碼器來修正錯誤。本論文結合了錯誤偵測電路，將收到的資料以錯誤偵測電路進行簡單的運算以判斷資料量是否受到干擾，如果沒有受到雜訊干擾，則直接輸出結果；如果有受到雜訊的干擾，就使用去尾迴旋解碼器解碼。
實驗結果顯示本論文提出的解碼器之存活記憶體單元比傳統解碼器約省60%以上的功率消耗，且再加上錯誤偵測電路後更可以省下整體功率消耗的55%~88%。因此，本論文所提出的方法的確可以讓維特比解碼器達到降低功率消耗的效果。

In wireless communication system, convolution code has been one of the most popular error-correcting code. To prevent from the interference of noise during transmission, the transmitter usually applies convolution encode to code the processed information, and the receiver will use Viterbi decoder to decode and correct the error bit to decrease the bit error rate. In 3G mobile communication, such decoder is often applied between the base station and the communication device as a decoding mechanism. Since traditional decoders of communication devices consume more than one third power of the whole receiver, the present study focuses on the way effectively reducing the power consumption of Viterbi decoder.
Traditional convolution coders use zero-tail, which make decoder be able to resist the interference of noise; however, this method would increase extra tail bits, which would decrease the code rate and affect the efficiency of transmission, especially for those information with short length, such as the header of packet. Tail-biting convolution code is another error-correcting code, which maintains the code rate, and it has been used in the control channel of LTE. Tail-biting convolution code is more complex than traditional decoder. Therefore, this thesis modifies the Wrap-Around Viterbi Algorithm (WAVA) to enormously decrease the power consuming while maintaining the bit error rate and the correctness of decoding. The aim of the present study is achieved by decreasing iteration number of WAVA algorithm to reduce one fourth of the whole power consumption.
On the other hand, if the received information is not interfered by noise, it’s unnecessary to turn on Tail-biting Convolution Decoder. As a result, the present study introduces the error detection circuit so that the received information can be simply decode and detected with the error detection circuit. If there is no noise interference, it can directly be outputted; if there is noise interference, however, it should be decoded by Tail-biting Convolution Decoder.
The experimental results show that the survivor memory unit saves more than 60% power than traditional decoders, moreover, it will save 55%~88% power consumption when it goes with the error detection circuit. Consequently, the proposed method is indeed able to reduce the power consumption of Tail-biting Convolution Decoder.
Keyword：wireless communication, tail-biting convolution code, code rate, Viterbi decoder, power consumption

摘要 i
Abstract ii
目錄 iv
表次 vi
圖次 vii
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機與方向 2
1.3 論文組織 3
第二章 去尾迴旋編碼之背景知識 5
2.1 迴旋碼 5
2.1.1 迴旋碼簡介 5
2.1.2 迴旋碼架構 6
2.2 維特比演算法與架構 9
2.2.1 維特比演算法 9
2.2.2 維特比解碼範例 11
2.2.3 追溯法 14
2.2.4 暫存器交換法 15
2.3 迴旋碼之錯誤偵測 16
2.3.1 錯誤偵測簡介 16
2.3.2 去尾迴旋碼簡介 18
第三章 去尾迴旋碼演算法 23
3.1 WAVA演算法的效果 23
3.2 修正iteration的取值方式 25
第四章 硬體架構 27
4.1 維特比解碼器硬體架構設計 27
4.2 錯誤偵測電路架構 32
第五章 驗證與實驗數據 38
5.1 Matlab雜訊通道模擬 38
5.2 矽智產驗證 41
5.3 硬體規格 42
5.4 實驗數據 43
第六章 結論與未來工作 51
參考文獻 52

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